Taiwan Semiconductor Manufacturing Comp. Ltd.

Wei Cheng Wu

Harry-Hak-Lay Chuang

Shih-Chang Liu

Meng-Han Lin

Chang-Ming Wu

Li-Feng Teng

Bao-Ru Young

Chia-Shiung Tsai

Te-Hsin Chiu

Chien-Hung Chang

Jui-Tsung Lien

Ya-Chen Kao

Yi Hsien Lu

Harry Hak-Lay Chuang

Ming Zhu

Ming Chyi Liu

Ru-Liang Lee

Po-Nien Chen

Chia Ming Liang

Meng-Fang Hsu

Fang-Lan Chu

Kong-Pin Chang

Alexander Kalnitsky

Chin-Yi Huang

Sheng-Chen Chung

Chen-Chin Liu

Yu-Hsiung Wang

Jyun-Ming Lin

Li-Jung Liu

Pai Chi Chou

Juo-Li Yang

Ching-Feng Fu

Wen-Tuo Huang

Jin-Aun Ng

Chih-Ren Hsieh

Shih-Ting Hung

Yu-Hsing Chang

Te-An Chen

Hak-Lay Chuang

Chih-Pin Huang

Chi-Hsun Hsieh

Eric Huang

Hong-Da Lin

Ku-Ning Chang

Yu-Chen Wang

Huan-Just Lin

Ming-Chyi Liu

Tzu-Yu Chen

Wei-Hang Huang

Yi-Ren Chen

Shih-Hao Lo

I-Ching Chen

Tsai-Chun Li

Kai-Shyang You

Hung-Pin Ko

Yu-Ling Hsu

Nuo Xu

Hsin Fu Lin

Ya-Chi Hung

Yuan-Jen Lee

Boa-Ru Young

Harry-Haklay Chuang

A method includes planarizing a protective layer over gate materials overlying a recessed region in a substrate. The planarizing includes forming a first planarized surface by planarizing a sacrificial layer over the protective layer, and forming a second planarized surface of the protective layer by etching the first planarized surface of the sacrificial layer at an even rate across the recessed region. An etch mask layer is formed over the second planarized surface, and control gate stacks are formed in the recessed region by etching the gate materials.

Method for improving control gate uniformity during manufacture of processors with embedded flash memory

A semiconductor package includes a first wafer comprising a first substrate, a first device structure, and a first bonding layer having a pattern of first bonding pads. The first bonding layer is disposed over the first substrate and the first device structure. The semiconductor package includes a second wafer comprising a second substrate, a second device structure, and a second bonding layer having a pattern of second bonding pads. The second bonding layer is disposed over the first bonding layer. The second device structure is disposed over the second bonding layer. The second substrate is disposed over the second device structure. The first bonding pads are each aligned with a corresponding one of the second bonding pads. The first device structure is electrically coupled to the second device structure, through at least one of the first bonding pads and at least one of the second bonding pads.

Semiconductor packages and methods of manufacturing thereof

Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.

Method to embed planar FETs with finFETs

In an embodiment, a method includes: receiving a first wafer and a second wafer, the first wafer including a first alignment mark, the first alignment mark including a first grid of first magnetic features, the second wafer including a second alignment mark, the second alignment mark including a second grid of second magnetic features; aligning the first alignment mark with the second alignment mark in an optical alignment process; after the optical alignment process, aligning the first alignment mark with the second alignment mark in a magnetic alignment process, north poles of the first magnetic features being aligned with south poles of the second magnetic features, south poles of the first magnetic features being aligned with north poles of the second magnetic features; and forming bonds between the first wafer and the second wafer.

Wafer bonding method and bonded device structure

In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Semiconductor device and manufacturing method thereof

A method of fabricating a semiconductor device includes forming first gate structure and a second gate structure over a core device region of a substrate. The method further includes forming stressors at opposite sides of the first gate structure. The method further includes doping the stressors to form a first source region and a first drain region of a first device. The method further includes doping into the substrate and at opposite sides of the second gate structure to form a second source region and a second drain region of a second device, wherein the first source region, the first drain region, the second source region and the second drain region are of a same conductivity, and the first source region comprises a different material from the second source region.

Method of manufacturing semiconductor device

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a source/drain region arranged within a substrate. A select gate and a memory gate are arranged over the substrate. An inter-gate dielectric structure is arranged between the memory gate and the select gate. A conductive contact is disposed on the source/drain region and vertically extends from a bottom of the select gate to a top of the select gate. The select gate is closer to the conductive contact than the memory gate. The select gate has a first outermost sidewall that faces away from the memory gate and a second outermost sidewall that faces the memory gate. The first outermost sidewall is taller than the second outermost sidewall.

Split gate memory device and method of fabricating the same

A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

Memory devices and method of fabricating same

The present disclosure relates integrated chip structure. The integrated chip structure includes one or more interconnects disposed within a dielectric structure over a substrate. A bond pad having a top surface is arranged along a top surface of the dielectric structure. The top surface of the bond pad includes a plurality of discrete top surface segments that are laterally separated from one another by non-zero distances that extend between interior sidewalls of the bond pad, as viewed in a cross-sectional view. The dielectric structure is disposed directly between the interior sidewalls of the bond pad.

Method of forming integrated chip structure having slotted bond pad in stacked wafer structure

A method is provided in which a monitor cell is made that is substantially identical to the flash memory cells of an embedded memory array. The monitor cell is formed simultaneously with the cells of the memory array, and so in certain critical aspects, is exactly comparable. An aperture is formed that extends through the control gate and intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination during a subsequent CMP process, a silicide protection layer (SPL), such as a resist protective oxide, is formed over exposed portions of the control gate prior to formation of a silicide contact formed on the floating gate. The SPL is formed simultaneously with existing manufacturing processes to avoid additional process steps.

Structure and method for preventing silicide contamination during the manufacture of micro-processors with embedded flash memory

In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first doped region and a second doped region disposed within a substrate. A ferroelectric material is arranged over the substrate and between the first doped region and the second doped region. An isolation structure is arranged within the substrate along a first side of the ferroelectric material. The isolation structure has a first width measured along an uppermost surface of the isolation structure and a second width measured along a horizontal line below the uppermost surface of the isolation structure. The second width is larger than the first width.

Embedded ferroelectric memory in high-k first technology

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a plurality of transistor devices disposed on or within a substrate and a plurality of memory devices disposed on or within the substrate. A first isolation structure is disposed within the substrate between the plurality of transistor devices and the plurality of memory devices. A dummy gate structure is arranged on the first isolation structure and has a top surface that is vertically above top surfaces of the plurality of transistor devices and the plurality of memory devices.

Boundary design to reduce memory array edge CMP dishing effect

In some embodiments, the present disclosure relates to a device that includes a silicon-on-insulator (SOI) substrate. A first semiconductor device is disposed on a frontside of the SOI substrate. An interconnect structure is arranged over the frontside of the SOI substrate and coupled to the first semiconductor device. A shallow trench isolation (STI) structure is arranged within the frontside of the SOI substrate and surrounds the first semiconductor device. First and second deep trench isolation (DTI) structures extend from the STI structure to an insulator layer of the SOI substrate. Portions of the first and second DTI structures are spaced apart from one another by an active layer of the SOI substrate. A backside through substrate via (BTSV) extends completely through the SOI substrate from a backside to the frontside of the SOI substrate. The BTSV is arranged directly between the first and second DTI structures.

3DIC structure for high voltage device on a SOI substrate

Various embodiments of the present application are directed to an IC device and associated forming methods. In some embodiments, a memory region and a logic region are integrated in a substrate. A memory cell structure is disposed on the memory region. A plurality of logic devices disposed on a plurality of logic sub-regions of the logic region. A first logic device is disposed on a first upper surface of a first logic sub-region. A second logic device is disposed on a second upper surface of a second logic sub-region. A third logic device is disposed on a third upper surface of a third logic sub-region. Heights of the first, second, and third upper surfaces of the logic sub-regions monotonically decrease. By arranging logic devices on multiple recessed positions of the substrate, design flexibility is improved and devices with multiple operation voltages are better suited.

Multi-type high voltage devices fabrication for embedded memory

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Zhubei, Taiwan

Wei Cheng Wu