Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

United Microelectronics Corp.

National Yang Ming Chiao Tung University

Au Optronics Corporation

Other

Wei-Cheng Wu

Chen-Hua Douglas Yu

Hsien-Wei Chen

Der-Chyang Yeh

Li-Han Hsu

Shang-Yun Hou

Shin-Puu Jeng

Chi-Hsi Wu

Cheng-Hsien Hsieh

Yen-Huei Chen

Tsung-Shu Lin

Hsien-Pin Hu

Wei Min Chan

Hung-Jen Liao

An-Jhih Su

Chih-Yu Lin

Kao-Cheng Lin

Tzu-Yu Wang

Harry-Hak-Lay Chuang

Tzuan-Horng Liu

Harry Hak-Lay Chuang

Ya-Chen Kao

Kuo-Ching Hsu

Li-Feng Teng

Chao-Hsiang Yang

Shih-Chang Liu

Ping-Wei Wang

Li-Hsien Huang

Tzu-Wei Chiu

Ying-Ju Chen

Chang-Ming Wu

Cheng-Chieh Hsieh

Wen-Tuo Huang

Chin-Chuan Chang

Sao-Ling Chiu

Ming Shih Yeh

Chang-Chia Huang

Chia-Shiung Tsai

Wen-Chih Chiou

Meng-Han Lin

Wei-Yu Chen

Meng-Fan Chang

Jonathan Tsung-Yung Chang

Yuan-Tai Tseng

Ru-Liang Lee

Te-Hsin Chiu

Chien-Chen Lin

Chien-Hung Chang

Alexander Kalnitsky

Chung-Jen Huang

Bang-Chiang Lan

Chien-Hsin Huang

Hui-Min Wu

Ping-Kang Huang

Wei-Min Chan

Chen-Shien Chen

Chih-Wei Lin

Hsiao-Tsung Yen

Ching-Hua Hsieh

Hidehiro Fujiwara

Charles Chew-Yuen Young

Chih-Hua Chen

Chen-Cheng Kuo

Yun-Han Lee

Jack Liu

Ku-Feng Yang

Chin-Chou Liu

Yung-Chi Lin

Ming Hung Tseng

Tsung-Yu Chen

William Wu Shen

Kim Hong Chen

Hsien-Hsin Sean Lee

Yu-Wei Lin

Yi-Hsiu Chen

Edward Yi Chang

Ching-Fang Chen

Chen-Hua Lin

Chin-Yi Huang

Jiun-Jye Chang

Chao-Yang Yeh

Shih-Peng Tai

Jun-Lin Yeh

Yu-Chen Hsu

Tzung-I Su

Bao-Ru Young

Ming Zhu

Chao-Wen Shih

Ming Chyi Liu

Kuo-Ching Huang

Hau-Tai Shieh

Chien-Yuan Chen

Yi-Tzu Chen

Sheng-Chen Chung

Wei Chuang Wu

Chih-Ren Hsieh

Yu-Hsing Chang

Henry Wang

Ming-I Wang

A memory device is provided which includes a first memory cell including a first transistor and a second transistor coupled to the first transistor in parallel. Gates of the first transistor and the second transistor are coupled to each other, and the gates of the first transistor and the second transistor pass different layers and overlap with each other. Types of the first transistor and the second transistor are the same.

Memory device

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer, and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

Semiconductor device and manufacturing method thereof

Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

Multi-stage bit line pre-charge

An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.

Device and method for UBM/RDL routing

Bonded wafer device structures, such as a wafer-on-wafer (WoW) structures, and methods of fabricating bonded wafer device structures, including an array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure. The array of contact pads formed in an interconnect level of at least one wafer may have an array pattern that corresponds to an array pattern of contact pads that is subsequently formed over a surface of the bonded wafer structure. The array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure may enable improved testing of individual wafers, including circuit probe testing, prior to the wafer being stacked and bonded to one or more additional wafers to form a bonded wafer structure.

Bonded wafer device structure and methods for making the same

A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.

Devices employing thermal and mechanical enhanced layers and methods of forming same

A method of forming an integrated circuit package includes following operations. A padding layer is formed on a portion of a carrier. A first semiconductor die is placed on the padding layer and a second semiconductor die is placed on the carrier. The first semiconductor die and the second semiconductor die are encapsulated with a first encapsulation layer. A first redistribution layer structure is formed over the first semiconductor die, the second semiconductor die and the first encapsulation layer. A third semiconductor die is placed on the first redistribution layer structure. The third semiconductor die is encapsulated with a second encapsulation layer. A second redistribution layer structure is formed over the third semiconductor die and the second encapsulation layer. The carrier is debonded. The padding layer is removed, and therefore, a recess is formed in the first encapsulation layer.

Method of forming an integrated circuit package having a padding layer on a carrier

A fan-out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.

Fan-out package having a main die and a dummy die

The present disclosure provides an electronic circuit, a memory device, and a method for operating an electronic circuit. An electronic circuit comprises a driver circuit configured to provide a drive voltage to a word line of the electronic circuit, a suppression circuit electrically connected to the driver circuit and the word line, and a control circuit electrically connected to the suppression circuit. The suppression circuit is configured to generate a voltage drop in the drive voltage. The control circuit controls the suppression circuit.

Electronic circuits, memory devices, and methods for operating an electronic circuit

A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.

Semiconductor package and manufacturing method thereof

Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.

Shared pad/bridge layout for a 3D IC

A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.

Stacked via structure disposed on a conductive pillar of a semiconductor die

A semiconductor device includes a circuit substrate, a semiconductor package, and a package frame. The semiconductor package is disposed on the circuit substrate. The package frame is disposed over the circuit substrate. The package frame encircles the semiconductor package. The semiconductor package has a first surface facing the circuit substrate and a second surface opposite to the first surface. The package frame leaves exposed at least a portion of the second surface of the semiconductor package. The package frame forms a cavity, which cavity encircles the semiconductor package.

A static random access memory includes a first and second memory cell array, a first word line, a bit line, a bit line bar, a primary driver circuit, and a first and second supplementary driver circuit. The first supplementary driver circuit is configured to pull a voltage of a first signal of the bit line or a second signal of the bit line bar to a first voltage level during a write operation in response to a supplementary driver circuit enable signal. The second supplementary driver circuit is configured to sense the voltage of the first or second signal. The second supplementary driver circuit includes a first pass-gate transistor. A first terminal of the first pass-gate transistor is coupled to a reference voltage supply. A second terminal of the first pass-gate transistor is electrically floating. A third terminal of the first pass-gate transistor is coupled to a first node.

Static random access memory with a supplementary driver circuit and method of controlling the same

Growing community of inventors

Hsinchu, Taiwan

Wei-Cheng Wu