Taiwan Semiconductor Manufacturing Comp. Ltd.

Wei-cheng Tzeng

Wei-Cheng Lin

Jiann-Tyng Tzeng

Shih-Wei Peng

Ching-Yu Huang

Szuya Liao

Cheng-Yin Wang

Jui-Chen Huang

A device including first nanosheet structures each including a first number of nanosheets, second nanosheet structures each including a second number of nanosheets that is different than the first number of nanosheets, and a plurality of rows including first rows and second rows. Where each of the first nanosheet structures is in a respective one of the first rows, each of the second nanosheet structures is in a respective one of the second rows, at least two of the first rows are adjacent one another, and at least two of the second rows are adjacent one another.

APR placement for hybrid sheet cells

A semiconductor device with isolation structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second FETs, an isolation structure, and a conductive structure. The first FET includes a first fin structure, a first array of gate structures disposed on the first fin structure, and a first array of S/D regions disposed on the first fin structure. The second FET includes a second fin structure, a second array of gate structures disposed on the second fin structure, and a second array of S/D regions disposed on the second fin structure. The isolation structure includes a fill portion and a liner portion disposed between the first and second FETs and in physical contact with the first and second arrays of gate structures. The conductive structure is disposed in the liner portion and conductively coupled to a S/D region of the second array of S/D regions.

Isolation structures in semiconductor devices

The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, a first active region disposed on the substrate, a first gate structure disposed on the first active region, and a second gate structure disposed on the first active region and spaced apart from the first gate structure. The first active region includes a first portion and a second portion, the first portion of the first active region and the second portion of the first active region collectively specify a first stair profile. The first stair profile is located between the first gate structure and the second gate structure from a top view.

Semiconductor device having active regions of different dimensions and method of manufacturing the same

A method is provided, including following operations: identifying a first contact via, a second contact via, or a combination thereof in a first standard cell, wherein the first contact via is coupled between a first active region and a first conductive line on a first side, and the second contact via is coupled between a second active region and a second conductive line on a second side; calculating a first cell height according to a first width of the first and second active regions, and calculating a second cell height according to a second width of the first and second active regions; calculating multiple first available cell heights based on a ratio between the first and second cell heights; generating layout designs of multiple first cells; and manufacturing at least first one element in the integrated circuit based on the layout designs of the first cells.

Growing community of inventors

TAIPEI, Taiwan

Wei-cheng Tzeng