Taiwan Semiconductor Manufacturing Comp. Ltd.

Keycore Technology Corp.

Au Optronics Corporation

Advanced Ion Beam Technology, Inc.

Tpo Displays Corporation

Chimei Innolux Corporation

Tsinghua University

Macronix International Co., Ltd.

Realtek Semiconductor Inc.

Novatek Microelectronics Corp.

Frontend Analog and Digital Technology Corporation

Comp-any Gmbh

Yang Yih Machinery Co., Ltd.

Nupoint Technology Co., Ltd.

Ipo Displays Corp

Wei-Cheng Lin

Jiann-Tyng Tzeng

Shih-Wei Peng

Kam-Tou Sio

Chih-Liang Chen

Charles Chew-Yuen Young

Wei-An Lai

Hui-Ting Yang

Chih-Ming Lai

Hui-Zhong Zhuang

Lipen Yuan

Cheng-Chi Chuang

Ru-Gun Liu

Te-Hsin Chiu

Lei-Chun Chou

Shih-Hsiu Tseng

Chien-Jen Hsiao

Chia-Tien Wu

Meng-Hung Shen

Chun-Ching Wei

Yang-En Wu

Li-Chun Tien

Guo-Huei Wu

Ching-Yu Huang

Yan-Hao Chen

Lee-Chung Lu

Yu-Xuan Huang

Pin-Dai Sue

Chew-Yuen Young

Wei-cheng Tzeng

Ching-Wei Tsai

Chun-Wen Cheng

Shi Ning Ju

Yi-Kan Cheng

Chun-Kuang Chen

Jack Liu

Kuan-Yu Chen

Yi-Hsun Chiu

Wei-Liang Lin

Yi-Shao Liu

Fei-Lung Lai

Shun Li Chen

Hsin-Chih Chen

Zhimin Wan

Chin-Yuan Tseng

Keiichi Sano

Fu-Yuan Hsueh

Shang-Wei Fang

Chien-Kuo Yang

Ta-Chuan Liao

Wei-Chen Chien

Chun-Hung Liou

Cheng-Ho Yu

Po-Wei Chiu

Praneeth Narayanasetti

Ming Chian Tsai

Hui-ting Yang

Kuan-Lun Cheng

Chih-Wei Chang

Huan-Chieh Su

Chun-Yuan Chen

Ting-Kuo Chang

Chun-Hsien Huang

Wei-Jung Lin

Kai-Chieh Yang

Yi-Bo Liao

Chung-Hsing Wang

Kam-tou Sio

Shih-Hsun Lo

Te-hsin Chiu

Jiun-Wei Lu

Meng-hung Shen

Chang-Ting Chung

Yang-Te Liang

Sheng-Ruei Hsu

Koulin Hu

Jay Yang

Wayne Lai

Chung-Hsin Liu

Ming-Han Lee

Hou-Yu Chen

Shang-Wen Chang

Yao-Wen Chang

Ya-Hsiang Tai

Lee-Hsun Chang

Yu-Wen Lin

Ting-Yu Chang

Hou-yu Chen

Ho-Hsiu Chou

Szuya Liao

Yi-Chang Shih

Chun-Yen Lin

Shin-Mu Tseng

Cheng-Yin Wang

Helen Shu-Hui Chang

Yu-Hao Hsu

Jui-Chang Lin

Yu-Jung Li

Hui-Ting Yang′

Fang-Hsing Wang

A method includes: forming a first channel structure through a first gate structure; forming a first source/drain structure coupled to the first channel structure at a first surface of the first gate structure; before the first source/drain structure is formed, forming a first isolation layer at a second surface of the first gate structure to isolate the first channel structure; and after the first source/drain structure is formed, forming a first insulation structure at a position of the first isolation layer. The first surface and the second surface are opposite to each other, and a size of the first insulation structure is equal to or larger than a size of the first source/drain structure.

Semiconductor device and manufacturing method thereof

A semiconductor device includes first and second conductive layers, a first epitaxial structure and a first via structure. The first conductive layer extends along a first direction, and provides a first reference voltage signal. The second conductive layer extends along the first direction, and is separated from the first conductive layer along a second direction. The first epitaxial structure is disposed between the first conductive layer and the second conductive layer, and has a first width along the first direction. The first via structure is disposed between the first conductive layer and the second conductive layer, and transmits the first reference voltage signal from the first conductive layer through the second conductive layer to the first epitaxial structure. The first via structure has a second width along the first direction. The second width is approximately equal to or larger than twice of the first width.

Semiconductor device

An integrated circuit (IC) includes first through fourth nano-sheet structures extending in a first direction and having respective first through fourth widths along a second direction perpendicular to the first direction, and first through fourth via structures electrically connected to corresponding ones of the first through fourth nano-sheet structures. The second width has a value greater than that of the third width. A width of the second via structure along the second direction has a value greater than that of a width of the third via structure along the second direction. The second and third nano-sheet structures are positioned between the first and fourth nano-sheet structures. The second and third via structures are configured to electrically connect the second and third nano-sheet structures to a first portion of a back-side power distribution structure configured to carry one of a power supply voltage or a reference voltage. The first and fourth via structures are configured to electrically connect the first and fourth nano-sheet structures to a second portion of the back-side power distribution structure configured to carry the other of the power supply voltage or the reference voltage.

Integrated circuit having hybrid sheet structure

A device including first nanosheet structures each including a first number of nanosheets, second nanosheet structures each including a second number of nanosheets that is different than the first number of nanosheets, and a plurality of rows including first rows and second rows. Where each of the first nanosheet structures is in a respective one of the first rows, each of the second nanosheet structures is in a respective one of the second rows, at least two of the first rows are adjacent one another, and at least two of the second rows are adjacent one another.

APR placement for hybrid sheet cells

An integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. The multiple backside conductive layers each includes conductive segments. The conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. The conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.

Backside conductive segments cover a first active region and define an opening above a second active region

Apparatus and methods for generating a physical layout for a high density routing circuit are disclosed. An exemplary semiconductor structure includes: a gate structure; a plurality of first metal lines formed in a first dielectric layer below the gate structure; at least one first via formed in a second dielectric layer between the gate structure and the first dielectric layer; a plurality of second metal lines formed in a third dielectric layer over the gate structure; and at least one second via formed in a fourth dielectric layer between the gate structure and the third dielectric layer. Each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines. Each of the at least one second via is electrically connected to the gate structure and a corresponding one of the plurality of second metal lines.

Methods for generating a circuit with high density routing layout

An integrated circuit includes a first power rail, a second power rail, and a power tap cell. The first power rail is at a first side of the integrated circuit. The second power rail is at a second side of the integrated circuit. The first and second sides are on opposite sides of at least a complementary field effect transistor. The power tap cell is coupled to the first power rail and the second power rail and configured to provide power from the first power rail to the second power rail.

Integrated circuits and methods for power delivery

A semiconductor device with isolation structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second FETs, an isolation structure, and a conductive structure. The first FET includes a first fin structure, a first array of gate structures disposed on the first fin structure, and a first array of S/D regions disposed on the first fin structure. The second FET includes a second fin structure, a second array of gate structures disposed on the second fin structure, and a second array of S/D regions disposed on the second fin structure. The isolation structure includes a fill portion and a liner portion disposed between the first and second FETs and in physical contact with the first and second arrays of gate structures. The conductive structure is disposed in the liner portion and conductively coupled to a S/D region of the second array of S/D regions.

Isolation structures in semiconductor devices

The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, a first active region disposed on the substrate, a first gate structure disposed on the first active region, and a second gate structure disposed on the first active region and spaced apart from the first gate structure. The first active region includes a first portion and a second portion, the first portion of the first active region and the second portion of the first active region collectively specify a first stair profile. The first stair profile is located between the first gate structure and the second gate structure from a top view.

Semiconductor device having active regions of different dimensions and method of manufacturing the same

An integrated circuit includes a plurality of first layer deep lines, a plurality of first layer shallow lines, a plurality of second layer deep lines, and a plurality of second layer shallow lines. The integrated circuit also includes a first active device and a second active device coupled between a conducting path that has a low resistivity portion and a low capacitivity portion. The first active device has an output coupled to a first layer deep line that is in the low resistivity portion. The second active device has an input coupled to a first layer shallow line that is in the low capacitivity portion. The low resistivity portion excludes the first layer shallow lines and the second layer shallow lines, and the low capacitivity portion excludes the first layer deep lines and the second layer deep lines.

Deep lines and shallow lines in signal conducting paths

An integrated circuit includes a first inverter and a first transmission gate constructed with wide type-one transistors and wide type-two transistors. The integrated circuit also includes a first clocked inverter constructed with narrow type-one transistors and narrow type-two transistors. A latch is formed with the first inverter and the first clocked inverter. The first transmission gate is connected to between an output of the first inverter. The wide type-one transistors are formed in a wide type-one active-region structure and the narrow type-one transistors are formed in a narrow type-one active-region structure. The wide type-two transistors are formed in a wide type-two active-region structure and the narrow type-two transistors are formed in in a narrow type-two active-region structure.

Integrated circuit having latch with transistors of different gate widths

The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device comprises a substrate, an isolation layer, a first electronic device, a first interconnection structure, a first conductive structure, and a second conductive structure. The substrate has a first surface and a second surface opposite the first surface. The isolation layer contacts the second surface of the substrate and has a first surface facing away from the substrate. The first electronic device is embedded in the substrate. The first interconnection structure extends from the first surface of the substrate to the first surface of the isolation layer. The first conductive structure is disposed on the first surface of the substrate. The second conductive structure contacts the first surface of the isolation layer. The first conductive structure and the second conductive structure are electrically connected by the first interconnection structure.

Semiconductor device including structure connecting frontside and backside metal and method of manufacturing the same

A monolithic three-dimensional (3D) integrated circuit (IC) device includes a lower tier including a lower tier cell and an upper tier arranged over the lower tier. The upper tier has a first upper tier cell and a second upper tier cell separated by a predetermined lateral space. A monolithic inter-tier via (MIV) extends from the lower tier through the predetermined lateral space, and the MIV has a first end electrically connected to the lower tier cell and a second end electrically connected to the first upper tier cell.

Three dimensional integrated circuit with monolithic inter-tier vias (MIV)

An integrated circuit with mixed poly pitch cells with a plurality of different pitch sizes is disclosed. The integrated circuit includes: at least a minimum unit each with at least a first number of first poly pitch cells with a first pitch size, and a second number of second poly pitch cells with a second pitch size, the first pitch size PP is different from the second pitch size PP1, the greatest common divisor of the first pitch size PP and the second pitch size PP1 is GCD, wherein GCD is an integer greater than 1; a gate length of the first pitch size is Lg; a gate length of the second pitch size is Lg1; Lg and Lg1 are capable of being extended to achieve G-bias for power and speed optimization of the minimum unit and the integrated circuit.

Mixed poly pitch design solution for power trim

A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.

Metal patterning for internal cell routing

Growing community of inventors

Taichung, Taiwan

Wei-Cheng Lin