Taiwan Semiconductor Manufacturing Comp. Ltd.

Keycore Technology Corp.

Au Optronics Corporation

Advanced Ion Beam Technology, Inc.

Tpo Displays Corporation

Chimei Innolux Corporation

Tsinghua University

Macronix International Co., Ltd.

Realtek Semiconductor Inc.

Novatek Microelectronics Corp.

Frontend Analog and Digital Technology Corporation

Comp-any Gmbh

Yang Yih Machinery Co., Ltd.

Nupoint Technology Co., Ltd.

Ipo Displays Corp

Wei-Cheng Lin

Jiann-Tyng Tzeng

Shih-Wei Peng

Kam-Tou Sio

Chih-Liang Chen

Charles Chew-Yuen Young

Wei-An Lai

Hui-Ting Yang

Chih-Ming Lai

Hui-Zhong Zhuang

Lipen Yuan

Cheng-Chi Chuang

Ru-Gun Liu

Te-Hsin Chiu

Lei-Chun Chou

Shih-Hsiu Tseng

Chien-Jen Hsiao

Chia-Tien Wu

Meng-Hung Shen

Chun-Ching Wei

Yang-En Wu

Li-Chun Tien

Guo-Huei Wu

Ching-Yu Huang

Yan-Hao Chen

Yu-Xuan Huang

Pin-Dai Sue

Chew-Yuen Young

Ching-Wei Tsai

Chun-Wen Cheng

Lee-Chung Lu

Shi Ning Ju

Chun-Kuang Chen

Jack Liu

Yi-Hsun Chiu

Wei-Liang Lin

Yi-Shao Liu

Fei-Lung Lai

Shun Li Chen

Hsin-Chih Chen

Zhimin Wan

Chin-Yuan Tseng

Keiichi Sano

Fu-Yuan Hsueh

Chien-Kuo Yang

Ta-Chuan Liao

Wei-Chen Chien

Chun-Hung Liou

Cheng-Ho Yu

Po-Wei Chiu

Praneeth Narayanasetti

Ming Chian Tsai

Wei-cheng Tzeng

Hui-ting Yang

Kuan-Lun Cheng

Chih-Wei Chang

Huan-Chieh Su

Yi-Kan Cheng

Chun-Yuan Chen

Ting-Kuo Chang

Chun-Hsien Huang

Kuan-Yu Chen

Wei-Jung Lin

Kai-Chieh Yang

Yi-Bo Liao

Shang-Wei Fang

Kam-tou Sio

Shih-Hsun Lo

Meng-hung Shen

Chang-Ting Chung

Yang-Te Liang

Sheng-Ruei Hsu

Koulin Hu

Jay Yang

Wayne Lai

Chung-Hsin Liu

Ming-Han Lee

Hou-Yu Chen

Shang-Wen Chang

Yao-Wen Chang

Ya-Hsiang Tai

Lee-Hsun Chang

Chung-Hsing Wang

Yu-Wen Lin

Ting-Yu Chang

Ho-Hsiu Chou

Hou-yu Chen

Yi-Chang Shih

Shin-Mu Tseng

Te-hsin Chiu

Helen Shu-Hui Chang

Jiun-Wei Lu

Cheng-Yin Wang

Yu-Hao Hsu

Jui-Chang Lin

Hui-Ting Yang′

Fang-Hsing Wang

Kuo-Pei Lu

Cheng-Liang Ma

Yuan-Ting Tseng

An integrated circuit includes a first power rail, a second power rail, and a power tap cell. The first power rail is at a first side of the integrated circuit. The second power rail is at a second side of the integrated circuit. The first and second sides are on opposite sides of at least a complementary field effect transistor. The power tap cell is coupled to the first power rail and the second power rail and configured to provide power from the first power rail to the second power rail.

Integrated circuits and methods for power delivery

A semiconductor device with isolation structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second FETs, an isolation structure, and a conductive structure. The first FET includes a first fin structure, a first array of gate structures disposed on the first fin structure, and a first array of S/D regions disposed on the first fin structure. The second FET includes a second fin structure, a second array of gate structures disposed on the second fin structure, and a second array of S/D regions disposed on the second fin structure. The isolation structure includes a fill portion and a liner portion disposed between the first and second FETs and in physical contact with the first and second arrays of gate structures. The conductive structure is disposed in the liner portion and conductively coupled to a S/D region of the second array of S/D regions.

Isolation structures in semiconductor devices

The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, a first active region disposed on the substrate, a first gate structure disposed on the first active region, and a second gate structure disposed on the first active region and spaced apart from the first gate structure. The first active region includes a first portion and a second portion, the first portion of the first active region and the second portion of the first active region collectively specify a first stair profile. The first stair profile is located between the first gate structure and the second gate structure from a top view.

Semiconductor device having active regions of different dimensions and method of manufacturing the same

An integrated circuit includes a plurality of first layer deep lines, a plurality of first layer shallow lines, a plurality of second layer deep lines, and a plurality of second layer shallow lines. The integrated circuit also includes a first active device and a second active device coupled between a conducting path that has a low resistivity portion and a low capacitivity portion. The first active device has an output coupled to a first layer deep line that is in the low resistivity portion. The second active device has an input coupled to a first layer shallow line that is in the low capacitivity portion. The low resistivity portion excludes the first layer shallow lines and the second layer shallow lines, and the low capacitivity portion excludes the first layer deep lines and the second layer deep lines.

Deep lines and shallow lines in signal conducting paths

An integrated circuit includes a first inverter and a first transmission gate constructed with wide type-one transistors and wide type-two transistors. The integrated circuit also includes a first clocked inverter constructed with narrow type-one transistors and narrow type-two transistors. A latch is formed with the first inverter and the first clocked inverter. The first transmission gate is connected to between an output of the first inverter. The wide type-one transistors are formed in a wide type-one active-region structure and the narrow type-one transistors are formed in a narrow type-one active-region structure. The wide type-two transistors are formed in a wide type-two active-region structure and the narrow type-two transistors are formed in in a narrow type-two active-region structure.

Integrated circuit having latch with transistors of different gate widths

The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device comprises a substrate, an isolation layer, a first electronic device, a first interconnection structure, a first conductive structure, and a second conductive structure. The substrate has a first surface and a second surface opposite the first surface. The isolation layer contacts the second surface of the substrate and has a first surface facing away from the substrate. The first electronic device is embedded in the substrate. The first interconnection structure extends from the first surface of the substrate to the first surface of the isolation layer. The first conductive structure is disposed on the first surface of the substrate. The second conductive structure contacts the first surface of the isolation layer. The first conductive structure and the second conductive structure are electrically connected by the first interconnection structure.

Semiconductor device including structure connecting frontside and backside metal and method of manufacturing the same

A monolithic three-dimensional (3D) integrated circuit (IC) device includes a lower tier including a lower tier cell and an upper tier arranged over the lower tier. The upper tier has a first upper tier cell and a second upper tier cell separated by a predetermined lateral space. A monolithic inter-tier via (MIV) extends from the lower tier through the predetermined lateral space, and the MIV has a first end electrically connected to the lower tier cell and a second end electrically connected to the first upper tier cell.

Three dimensional integrated circuit with monolithic inter-tier vias (MIV)

An integrated circuit with mixed poly pitch cells with a plurality of different pitch sizes is disclosed. The integrated circuit includes: at least a minimum unit each with at least a first number of first poly pitch cells with a first pitch size, and a second number of second poly pitch cells with a second pitch size, the first pitch size PP is different from the second pitch size PP1, the greatest common divisor of the first pitch size PP and the second pitch size PP1 is GCD, wherein GCD is an integer greater than 1; a gate length of the first pitch size is Lg; a gate length of the second pitch size is Lg1; Lg and Lg1 are capable of being extended to achieve G-bias for power and speed optimization of the minimum unit and the integrated circuit.

Mixed poly pitch design solution for power trim

A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.

Metal patterning for internal cell routing

The present disclosure provides a semiconductor device. The semiconductor device includes: a first cell, a dielectric layer, and a snorkel structure. The first cell has an output terminal. The dielectric layer is disposed on the first cell. The snorkel structure is disposed in the dielectric layer. The snorkel structure includes a first conductive structure, a first conductive layer, and a second conductive structure. The first conductive layer is electrically connected to the output terminal of the cell. The first conductive layer is disposed on and electrically connected to the first conductive structure. The second conductive structure is disposed on and electrically connected to the first conductive layer. The second conductive structure has a topmost conductive layer buried in the dielectric layer.

Semiconductor device and method of failure analysis for semiconductor device

A circuit includes a first metal layer having a first first metal layer strip adjacent to a first boundary and a second first metal layer strip adjacent to a second boundary opposite to the first boundary. The first and second first metal layer strips, the first boundary, and the second boundary are parallel to each other. The circuit further includes a second metal layer having a first second metal layer strip and a second second metal layer strip adjacent to the first second metal layer strip. The first second metal layer strip is connected to the first metal layer strip at the first first metal layer strip and the second second metal layer strip is connected to the first metal layer strip at the second first metal layer strip. Each of the first and the second second metal layer strips are parallel to each other.

Layout architecture for a cell

Apparatus and methods for back side routing a data signal in a semiconductor device are described. In one example, a described semiconductor cell structure includes: a dummy device region at a front side of the semiconductor cell structure; a metal layer including a plurality of metal lines at a back side of the semiconductor cell structure; a dielectric layer formed between the dummy device region and the metal layer; an inner metal disposed within the dielectric layer; at least one first via that is formed through the dielectric layer and electrically connects the inner metal to the plurality of metal lines at the back side; and at least one second via that is formed in the dielectric layer and physically coupled between the inner metal and the dummy device region at the front side.

Back side signal routing in a circuit with a relay cell

A method is provided, including following operations: identifying a first contact via, a second contact via, or a combination thereof in a first standard cell, wherein the first contact via is coupled between a first active region and a first conductive line on a first side, and the second contact via is coupled between a second active region and a second conductive line on a second side; calculating a first cell height according to a first width of the first and second active regions, and calculating a second cell height according to a second width of the first and second active regions; calculating multiple first available cell heights based on a ratio between the first and second cell heights; generating layout designs of multiple first cells; and manufacturing at least first one element in the integrated circuit based on the layout designs of the first cells.

Integrated circuit device and manufacturing method of the same

A method includes fabricating a first-voltage underlayer power rail conductively connecting to the source region of a first-type transistor and fabricating a second-voltage underlayer power rail conductively connecting to the source region of a second-type transistor. Each of the first-voltage and second-voltage underlayer power rails extends in a first direction. The method also includes patterning a first connection layer to form a first-voltage power rail and a second-voltage power rail extending in the second direction which is perpendicular to the first direction. The first-voltage power rail is directly connected with the first-voltage underlayer power rail through a first via-connector and the second-voltage power rail is directly connected with the second-voltage underlayer power rail through a second via-connector.

Power rail and signal conducting line arrangement

One aspect of this description relates to a method for operating an integrated circuit (IC) manufacturing system. The method includes placing a first nano-sheet structure within a IC layout diagram. The first nano-sheet structure has a first width. The method includes abutting a second nano-sheet structure with the first nano-sheet structure. The second nano-sheet structure has a second width. The second width is less than the first width. The method includes generating and storing the IC layout diagram in a storage device.

Variable width nano-sheet field-effect transistor cell structure

Growing community of inventors

Taichung, Taiwan

Wei-Cheng Lin