Macronix International Co., Ltd.

Other

Wistron Corporation

Industrial Technology Research Institute

Wei-Chen Wang

Yuan-Hao Chang

Tei-Wei Kuo

Chien-Chung Ho

Yung-Chun Li

Hung-Sheng Chang

Tsung-Hsien Chen

Chia-Cheng Su

Po-Yuan Hsu

Hsing-Wang Chang

Ping-Hsien Lin

Tse-Yuan Wang

Hsiang-Pang Li

Han-Wen Hu

Chorng-Kuang Wang

Huai-Mu Wang

Ming-Hsiung Huang

Shu-Yin Ho

Chun-Feng Wu

Che-Wei Tsao

Shu-Hsien Liao

Kuang-Hu Huang

Ting-Hsuan Lo

Ten-Long Dan

An operation method of an artificial neural network is provided. The operation method includes: dividing input information into a plurality of sub-input information, and expanding kernel information to generate expanded kernel information; performing a Fast Fourier Transform (FFT) on the sub-input information and the expanded kernel information to respectively generate a plurality of frequency domain sub-input information and frequency domain expanded kernel information; respectively performing a multiplying operation on the frequency domain expanded kernel information and the frequency domain sub-input information to respectively generate a plurality of sub-feature maps; and performing an inverse FFT on the sub-feature maps to provide a plurality of converted sub-feature maps for executing a feature extraction operation of the artificial neural network.

Operation method for artificial neural network

An embodiment of the present disclosure discloses a memory device. The memory device comprises a memory controller, a buffer and a memory array. The buffer is coupled to the memory controller or embedded in the memory controller. A storage space of the buffer is configured by the memory controller to include a plurality of groups. The memory array is coupled to the memory controller, and comprising a plurality of tiles. The groups are one-to-one corresponding to the tiles. Each of the groups is configured to store data to be written into the corresponding tile. The memory controller performs one or more write operations based on the groups.

Memory device and operation method thereof

An in-memory computing method and apparatus, adapted for a processor to perform MAC operations on a memory, are provided. In the method, a format of binary data of weights is transformed from a floating-point format into a quantized format by truncating at least a portion of fraction bits of the binary data and calculating complements of remaining bits, and programming the transformed binary data into cells of the memory. A tuning procedure is performed by iteratively inputting binary data of input signals into the memory, integrating outputs of the memory, and adjusting the weights programmed to the cells based on the integrated outputs. The binary data of the weights is reshaped based on a probability of reducing bits with a value of one in the binary data of each weight. The tuning procedure is repeated until an end condition is met.

In-memory computing method and apparatus

A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.

Memory device and operating method thereof

Disclosed is a memory device and an operation method thereof. The operation method of memory device, comprising: programming a plurality of sub-matrices including at least one of non-zero element of a rearranged matrix to a plurality of operation units of the memory device; and programming a mapping table into a working memory of a memory device. The rearranged matrix is generated by rearrange a plurality of columns and a plurality of rows of an original matrix according to the positions of a plurality of non-zero elements of the original matrix. The mapping table comprises a correspondence of row indexes between the original matrix and the rearranged matrix, a correspondence of column indexes between the original matrix and the rearranged matrix and a correspondence between the sub-matrices including at least one non-zero element and the operation units storing the sub-matrices including at least one non-zero element.

A memory device includes: a memory array used for implementing neural networks (NN); and a controller coupled to the memory array. The controller is configured for: in updating and writing unrewritable data into the memory array in a training phase, marching the unrewritable data into a buffer zone of the memory array; and in updating and writing rewritable data into the memory array in the training phase, marching the rewritable data by skipping the buffer zone.

Memory device and wear leveling method for the same

A memory device includes: a memory array used for implementing neural networks (NN), the NN including a plurality of layers; and a controller coupled to the memory array, the controller being configured for: determining a computation duration of a first data of a first layer of the plurality of layers; selecting a first program operation if the computation duration of the first data of the first layer is shorter than a threshold; and selecting a second program operation if the computation duration of the first data of the first layer is longer than the threshold, wherein the second program operation has a longer program pulse time than the first program operation.

Memory device for neural networks

A data management method for a memory is provided. The memory includes memory pages. Each of the memory pages includes memory cells. A data update command corresponding to a logical address is received. The logical address maps to a physical address of a target memory page before receiving the data update command. First and second reading voltages are applied to obtain at least a first and a second target memory cell to be sanitized in the target memory page of the memory pages, a first programming voltage is applied to change the logical state of the first target memory cell to a logical state with a higher threshold voltage, and a second programming voltage is applied to change the logical state of the second target memory cell to a logical state with a higher threshold voltage. The first programming voltage is different from the second programming voltage.

Data management method for memory and memory apparatus using the same

The present disclosure provides a memory system, a method of operating memory, and a non-transitory computer readable storage medium. The memory system includes a memory chip and a controller. The controller is coupled with the memory chip, which the controller is configured to: receive a first data corresponding to a first version from a file system in order to store the first data corresponding to the first version in a first page of the flash memory chip; and program the first data corresponding to a second version in the first page in response to the first data of the second version, which the second version is newer than the first version.

Memory system, method of operating memory, and non-transitory computer readable storage medium

A memory management method includes: performing a bloom filtering operation on a plurality of logic block addresses to determine a read and written frequency of each of the logic block addresses; setting a first program/erase (P/E) cycle threshold and a second P/E cycle threshold value, wherein the first P/E cycle threshold value is smaller than the second P/E cycle threshold value; dividing each of physical memory blocks into a first type memory block, a second type memory block or a third type memory block according to the first P/E cycle threshold value and the second P/E cycle threshold value; and, allocating each of the logic block addresses to the first type memory block, the second type memory block or the third type memory block according to the read and written frequency of corresponding logic block addresses.

Memory management apparatus and memory management method

A multifunction dumbbell includes a handle having two projections on both ends respectively; two hollow weight members each having a protrusion extending toward the handle; two spacer sleeves each having a closed flange fixedly secured to a joining portion of the handle and either projection, with the spacer sleeves fixedly fastened between the protrusions and the projections; two rings each having an inner diameter less than an outer diameter of the weight member so that the rings can be put on the weight members and retained thereon respectively; two half-spherical members each fixedly secured to the ring and complimentarily engaged with the weight member; and two truncated conic springs each put on the protrusion and a portion of the weight member to be retained between the spacer sleeve and the ring. The rings and the half-spherical members together are adapted to rotate about the weight members.

Multifunction dumbbell

An electronic apparatus includes a machine body, a stylus, and a cord retractor. The machine body includes a housing and an electronic component module mounted in the housing. The cord retractor includes an inner axle mounted in one of the stylus and the housing, a spool rotatably sleeved around the inner axle, a biasing component mounted between the inner axle and the spool, and having a pair of ends connected respectively to the inner axle and the spool such that the spool is operated to rotate resiliently relative to the inner axle, and a connecting cord wound around the spool and that may be unwound therefrom, and having a first end connected to the housing and a second end connected to the stylus. An assembly of a cord retractor and a stylus is also disclosed.

Electronic apparatus having a stylus with a cord retractor connected thereto and an assembly of a cord retractor and a stylus

A waterproof mechanism includes a housing having a base wall, at least one door plate, a first waterproof seal, and at least one return spring. The base wall is formed with an opening. The door plate is connected movably to the base wall for closing the opening in the base wall. The door plate is pushable to perform a motion relative to the base wall to thereby open the opening. The first waterproof seal is disposed between the base wall and the door plate and around the opening so as to establish a water-tight seal between the base wall and the door plate. The return spring is disposed between the base wall and the door plate for biasing the door plate to close the opening.

Waterproof mechanism and electronic device having the same

A jogging exerciser includes two a base having an upright, two handles connected to two friction wheels at opposite sides on the upright, a locating pin for fixing the handles to the upright to stop the handles from turning with the friction wheels, a crank revolvably supported on the upright, a driving wheel turned with the crank, a flywheel coupled to the driving wheel, and two parallel sliding bars slidably supported on a rack at the rear side of the base and having pivoted to both ends of the crank.

Jogging exerciser

A transceiver has a pulse position modulation (PPM) encoder, automatic gain control (AGC) circuit and timing recovery circuit. The PPM encoder illustratively has a frequency divider, slot selector, and mixer. The frequency divider divides the frequency of a clock signal to which the data of the non-return to zero (NRZ) signal are aligned to produce a half frequency clock signal. The slot selector selects pulses of the clock signal and the half frequency clock signal depending on logic values of the NRZ signal and a control signal to produce first and second slot selected signals. The mixer mixes the first and second slot selected signals to produce a PPM signal of the NRZ signal. The AGC circuit illustratively has a variable gain amplifier, a hysteresis comparator, an event detector, a timer, and a counter. The variable gain amplifier amplifies the PPM signal using a dynamically adjusted gain that depends on an inputted digital control value. The counter increments the inputted digital control value according to a clock signal outputted from the timer to increase the gain. The hysteresis comparator detects a signal level of the amplified PPM signal. The event detector causes the counter to decrease the inputted digital control value if the signal level is outside of a predetermined signal level range. The timing recovery circuit has a frequency track, a slot locked loop and a phase locked loop. The frequency track generates a coarse clock fx having a frequency that depends on a frequency of the PPM signal. The slot locked loop generates a resampling clock signal having a frequency that depends on the course clock fx and having slots locked to slots of the PPM signal. The phase locked loop locks a phase of the coarse clock fx to a phase of the PPM signal.

Growing community of inventors

Taipei, Taiwan

Wei-Chen Wang