Schlumberger Technology Corporation

Silergy Semiconductor Technology (hangzhou) Ltd

Zhejiang Bangsun Technology Co., Ltd.

Smith International, Inc.

Zhejiang University

Hangzhou Hikvision Digital Technology Co., Ltd.

Advanced New Technologies Co., Ltd.

Hangzhou City University

Hangzhou Hikvision System Technology Co., Ltd.

Semitronix Corporation

Tunghsu Optoelectronic Technology Co., Ltd.

Vivachek Biotech (hangzhou) Co., Ltd.

Huzhou Mingshuo Optoelectronics Technology Co., Ltd.

Ning Bo Eye Hospital

Huzhou Mingshuo Optoelectronic Technology Co., Ltd.

Wei Chen

Yuelin Shen

Sujian Huang

Zhengxin Zhang

Chen Zhao

Yu Qi

Zhenyu Chen

Qiqian Lin

Riadh Boualleg

Gang Xu

Richard John Harmer

Tao Huang

Liming Wang

Yang Gao

Ping Zhang

Martin D Hurlimann

Xiaodong Huang

Lucian K Johnston

Wei Jiang

Jian Zhang

Weichun Wang

Shin Utsuzawa

Chiqing Fang

Jibin Shi

Zhen Sun

Gang Wang

Christopher Bogath

Youtong Fang

Jiabin Liu

Yang Xu

Fan Lan

Jian Wei

Wenhu Kan

Jinming Duan

Liangrong Lin

Xiaoyan Huang

Heran Li

Yani Dong

Xingen Wang

Xinyu Wang

Ping Lu

Rongbing Chen

Lu Jin

Yuewen Xu

Geng Yun

Hansong Xiao

Li Cao

Jiancheng Zhang

Yufei Dong

Antoine Marcel Benard

Guishui Zheng

Gao Fan

Ludan Yang

Zhongwen Li

Qinxiang Zheng

Dongxu Li

Vasileios Varveropoulos

Chanhui Bin

LiBin Zhou

Zhiyong Ding

Jien Ma

Jiabai Cheng

Qinfen Lu

Maria Neves Carrasquilla

Yuquan Chen

My Lien Ta

Jiahong Xie

Gregg Alexander

Haoxin Cui

Libin Zhou

Qing Li

A digital isolator can include: an encoding circuit configured to receive an input digital signal, and to encode a rising edge and a falling edge of the input digital signal into different coded signals; an isolating element coupled to encoding circuit, and being configured to transmit the coded signal in an electrical isolation manner; and a decoding circuit configured to receive the coded signal through the isolation element, and to decode the coded signal to obtain the rising edge and the falling edge, in order to output an output digital signal consistent with the input digital signal, where the rising edge of the input digital signal is encoded as a first pulse sequence, and the falling edge of the input digital signal is encoded as a second pulse sequence different from the first pulse sequence.

Digital isolator and digital signal transmission method thereof

A lumped power supply circuit for converting an AC signal into a DC signal, the lumped power supply circuit including: a cascaded H-bridge circuit having N H-bridge sub-circuits connected in series between two input terminals of the AC signal, and being configured to convert the AC signal into N first voltage signals, where N is a positive integer greater than or equal to 2; a high-frequency filtering module configured to filter the N first voltage signals, and to generate N second voltage signals; a DC conversion module to receive the N second voltage signals, and to convert the N second voltage signals into at least one third voltage signal; and a lumped power buffer module having an output terminal coupled to a load, and being configured to receive the at least one third voltage signal, and to filter out part of power frequency fluctuations in the third voltage signal.

Lumped power supply circuit for converting an AC signal into a DC signal

A multilevel self-balance control circuit can include: a voltage divider unit configured to receive and divide an input voltage; a voltage-controlled charge source load coupled to an output terminal of the voltage divider unit, and being configured to adaptively adjust charge amount input to the voltage-controlled charge source load based on an output voltage of the voltage divider unit, such that a total amount of charges flowing through the voltage-controlled charge source load during a period of each working state of the voltage divider unit is positively correlated with the output voltage of the voltage divider unit, thereby forming a negative feedback loop to achieve voltage balancing of the voltage divider unit; and a control unit configured to generate control signals for the voltage divider unit and the voltage-controlled charge source load, thereby coordinately controlling the voltage divider unit and the voltage-controlled charge source load.

Multilevel self-balance control circuit, DC/DC conversion system and AC/DC conversion system

Smart bird feeder

A cascade circuit can include: N power conversion units connected in series between two ports of a power supply, where N is a positive integer greater than or equal to 2; a controller connected to one of the N power conversion units, and being configured to send a signal to be transmitted through the connected power conversion unit; where each of the power conversion units is configured to send the signal to be transmitted to a next-stage power conversion unit when the each of the power conversion unit shares a reference voltage with the adjacent next-stage power conversion unit; and where the signal to be transmitted is controlled to be transmitted from a previous-stage power conversion unit to a next-stage power conversion unit in sequence until the signal to be transmitted is received by all of the N power conversion units.

Cascade circuit, control method and integrated circuit thereof

Bird feeder

An artificial intelligence eye disease screening and diagnostic system based on an ophthalmic robot, comprising a human eye positioning analysis module, an image information collection module, an AI picture quality monitoring module, an eye disease analysis and diagnosis module, a data storage management module, and an execution control module. The system can replace ophthalmologists to perform eye disease diagnosis tasks in regions lacking ophthalmologists, and assists the ophthalmologists in eye disease screening and diagnosis in large hospitals with a large number of patients, thus improving diagnosis efficiency.

Artificial intelligence eye disease screening and diagnostic system based on ophthalmic robot

A fast processing method of massive time-series data based on aggregated edges and time-series aggregated edges implements fast and real-time processing based on an association of a graph data structure under a massive data pattern. In terms of incremental flow calculation based on time windows, the present disclosure proposes an innovative data structure of 'aggregated edge' and “time-series aggregated edge”, which is suitable for data modeling of real-time dynamic graph. The present disclosure introduces a time-series graph query language, which adds descriptive semantics of time series information, and not only supports basic queries based on vertices, edges, and attributes, but also can implement users' graph queries for index calculation results in a time window. The graph query includes graph matching and graph filtering. The present disclosure is especially suitable for fields such as marketing and real-time risk control based on massive data mining and has good timeliness control and high scalability.

Fast processing method of massive time-series data based on aggregated edge and time-series aggregated edge

Disclosed is a method for separating and preparing delphinidin-3-O-(6″-O-p-coumaroyl) glucoside. By means of extraction, macroporous resin purification, extraction, preparative liquid chromatography and high-speed countercurrent chromatography and the like, a high-purity delphinidin-3-O-(6″-O-p-coumaroyl) glucoside monomer can be obtained from grapes by separation and purification. By means of this method, at least 80 mg of delphinidin-3-O-(6″-O-p-coumaroyl) glucoside can be obtained from 10 kg of grape skins, with the purity can be no less than 98%. The method has the advantages of simple operation, large handling capacity, good repeatability, etc., which provides a new idea for the development and utilization of grape resources.

Method for preparing delphinium acylated anthocyanin

A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

Addressable test chip test system

Provided is an aggregation index structure and an aggregation index method for improving aggregation query efficiency. The aggregation index partitions streaming data through two dimensions of grouping and slicing, and then aggregates the partitioned data. The structure includes index metadata, a sliced data list and a detailed data store; the aggregation index method includes three parts: aggregation index definition, aggregation index creation and aggregation index query. The aggregation index structure and method provided by the present disclosure can greatly improve the efficiency of aggregation query, support the ad hoc aggregation query of PB-level data, complete the aggregation query of a large amount of data in seconds, support the insertion of new data at any time, and return the query results in minutes or even seconds latency in the event of changes of the query range conditions.

Structure and method of aggregation index for improving aggregation query efficiency

Provided is a method for reverse real-time matching based on event-driven graph patterns. The method includes definition of a graph pattern, establishment of reverse matching architecture and a reverse matching method; and the graph pattern is used for describing a spatial connection relationship among vertices and edges in a graph in a reverse order and attribute constraints thereof, and includes a linked list of matching steps and matching contexts. Reverse real-time matching of the graph pattern is realized according to the reverse matching architecture, and the problem of event-driven subgraph matching in a real-time scene is solved.

Method for reverse real-time matching based on event-driven graph patterns

Dog cage

An alternating current to direct current conversion circuit includes a rectifier circuit, a first DC to DC conversion module and a second DC to DC conversion module. The first DC to DC conversion module includes multiple power switches and an inductor and is coupled between the rectifier circuit and the second DC to DC conversion module. Multiple power switches in the first DC to DC conversion module are controlled to be turned on simultaneously, so that a voltage across each of the power switches in the first DC to DC conversion module is reduced. The alternating current to direct current conversion circuit includes no power switch with a high withstand voltage, so that the alternating current to direct current conversion circuit has a small volume, low switching loss, less energy loss, and good heat dissipation, thereby increasing power density.

Alternating current to direct current conversion circuit

An alternating current to direct current conversion circuit includes N first power converters instead of a boost circuit including a power switch with a high withstand voltage. The N first power converters each have an input end and theses input ends are connected in series, to perform power factor correction. Therefore, the alternating current to direct current conversion circuit includes no power switch with a high withstand voltage, so that the alternating current to direct current conversion circuit has a small volume, low switching loss, less energy loss, and good heat dissipation, thereby increasing power density.

Growing community of inventors

Zhejiang, China

Wei Chen