Phison Electronics Corporation

Wei-Chen Teo

Chien-Hua Chu

Chih-Kang Yeh

Ming-Jen Liang

Ban-Hui Chen

Min-Cheng Wang

Pi-Chi Yang

A memory erasing method and a memory controller and a memory storage apparatus using the same are provided. The method comprising establishing a link list according to a plurality of physical blocks of a spare area, and storing the link list into the rewritable non-volatile memory module, wherein the physical blocks of the spare area are recorded in the link list according to an arrangement order; and during every power on of the memory storage apparatus, selecting a plurality of third physical blocks among the physical blocks in the spare area according to the link list and a predetermined number, and respectively executing an erase command on the third physical blocks, wherein the third physical blocks are arranged at a beginning of the link list, and the number of the third physical blocks is the predetermined number.

Memory erasing method, memory controller, and memory storage apparatus

A memory erasing method and a memory controller and a memory storage apparatus using the same are provided. The memory erasing method includes following steps. Physical blocks of a rewritable non-volatile memory module of the memory storage apparatus are logically grouped into at least a data area and a spare area. After the memory storage apparatus is powered on, an erase mark is configured for each of the physical blocks in the spare area, and each of the erase marks is initially set to an unerased state. After the memory storage apparatus enters a standby state, whether an erase command is executed on the physical blocks in the spare area is determined according to the erase marks. Thereby, the memory erasing method can effectively shorten the time for the memory storage apparatus to enter the standby state after the memory storage apparatus is powered on.

A memory storage device, a memory controller thereof, and a method for programming data thereof are provided. The memory storage device having an error checking and correcting (ECC) circuit and a rewritable non-volatile memory chip is coupled to a host system. The method includes determining whether write data to be written into the rewritable non-volatile memory chip belongs to a specific type. The method also includes generating at least one first type ECC code with a first length by the ECC circuit according to the write data if the write data belongs to the specific type. The method further includes generating at least one second type ECC code with a second length by the ECC circuit according to the write data if the write data does not belong to the specific type. In which, the first length is longer than the second length.

Memory storage device, memory controller thereof, and method for programming data thereof

A memory storage device, a memory controller thereof, and a method for programming data thereof are provided. The memory storage device includes a buffer memory and a rewritable non-volatile memory chip, wherein the rewritable non-volatile memory chip includes a buffer unit and a plurality of physical blocks. The method includes storing first data received from a host system into the buffer memory, and generating a writing complete message for replying to the host system after the first data stored in the buffer memory is transmitted to the buffer unit by using a first data transmitting command. The method further includes programming the first data to a first physical block of the physical blocks. Meanwhile, if a data program failure is detected, the method also includes programming the first data maintained in the buffer unit to a second physical block by using a second data transmitting command.

A memory management table processing method for storing a plurality of entries belonging to a plurality of memory management tables into a buffer memory of a memory storage apparatus is provided, wherein each of the entries has at least one invalid bit. The present method includes following steps. An area corresponding to each of the memory management tables is configured in the buffer memory. Invalid bit information corresponding to each of the memory management tables is recorded. The invalid bit in each of the entries is removed according to the invalid bit information corresponding to each of the memory management tables, so as to generate a valid data stream corresponding to each of the entries. Each of the valid data streams is written into the corresponding area in the buffer memory. Accordingly, the storage space of the buffer memory can be efficiently utilized.

Memory management table processing method, memory controller, and memory storage apparatus

A memory storage device, a memory controller, and a method for identifying a valid data are provided. A rewritable non-volatile memory chip of the memory storage device includes physical blocks. Each of the physical blocks has physical pages. In the present method, logical blocks are configured and mapped to a portion of the physical blocks, wherein each of the logical blocks has logical pages. When a data to be written by a host system into a specific logical page is received, a substitute physical block is selected, the data is written into a specific physical page in the substitute physical block, and the address of a physical page in which a previous data corresponding to the specific logic page is written is recorded into the specific physical page. Thereby, a physical page containing the latest valid data can be identified among several physical pages corresponding to a same logical page.

Memory storage device, memory controller, and method for identifying valid data

A data merging method for merging data belonging to a first logical block in a rewritable non-volatile memory module is provided. The method includes getting a second physical block from a free area of the rewritable non-volatile memory module and determining whether a valid logical page number is smaller than a predetermined number. The method also includes, when the valid logical page number is smaller than the predetermined number, storing a corresponding page mapping table in a start physical page of the second physical block and writing at least one valid page data belonging to the first logical block into at least one physical page of the second physical block. Accordingly, the method can effectively shorten the time for merging data.

Data merging method for non-volatile memory and controller and storage apparatus using the same

A data reading method suitable for a flash memory storage system having a flash memory is provided, wherein the flash memory is substantially divided into a plurality of blocks and these blocks are grouped into at least a data area and a spare area. The data reading method includes: respectively determining whether the blocks in the data area are frequently read blocks; allocating a buffer storage area corresponding to the frequently read block and copying data stored in the frequently read block to the buffer storage area; and reading the data from the buffer storage area corresponding to the frequently read block when the data stored in the frequently read block is to be read. As described above, data loss caused by read disturb can be effectively prevented.

Data reading method for flash memory and controller and storage system using the same

A flash memory controller having a flash memory testing functions is provided, in which the flash memory controller includes a microprocessor unit, a flash memory interface unit, a host interface unit and a memory cell testing unit. The flash memory interface unit is configured for connecting a plurality of flash memory chips, where each flash memory chip has a plurality of flash memory dies and each flash memory die has a plurality of physical blocks. The host interface unit is configured for connecting a host system. The memory cell testing unit is configured for determining whether the physical blocks can be normally written, read and erased. Accordingly, the flash memory controller can perform a flash memory testing under a command of the host system and all the physical blocks of the flash memory chip can be tested during the flash memory testing.

Controller having flash memory testing functions, and storage system and testing method thereof

A data writing method for a block of a multi level cell NAND flash memory including upper page addresses and lower page addresses is provided, wherein a writing speed at the lower page addresses is higher than that at the upper page addresses. The data writing method includes receiving a writing command and determining whether an address to be written with new data in the writing command is the upper page address of the block. The method also includes copying old data previously recorded on the lower page addresses of the block as an old data backup when the address to be written in the writing command is the upper page address of the block and then writing the new data to the address to be written. Thus, old data may be protected while writing data to the upper page address of the multi level cell NAND flash memory.

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Miaoli County, Taiwan

Wei-Chen Teo