Silicon Integrated Systems Corporation

Industrial Technology Research Institute

Wei-Chen Shen

Hung-Chih Liu

Ming-Jer Chen

Po-Chin Hsu

Tien-Yu Wu

Hung-chih Liu

Sheng-Yeh Lai

Chu-Chang Lin

Chi-Tai Yao

Yen-Bin Gu

A DC offset canceling circuit. The DC offset canceling circuit applied in a variable gain amplifier includes chopper circuits, a transconductance amplifier, and at least one internal capacitor. The transconductance amplifier and at least one capacitor function as a filter for canceling DC offset of the variable gain amplifier. A first chopper circuit is inserted between the output of the variable gain amplifier and the input of the transconductance amplifier. A second chopper circuit is inserted between the output of the transconductance amplifier and the capacitor. The DC offset and low frequency noise of the transconductance amplifier, the undesired signal, is translated up to a chopping frequency by chopper circuits. The chopping frequency is much higher than the desired signal bandwidth, and the amount of the undesired signal in the passband of the signal is thereby greatly reduced.

DC offset canceling circuit applied in a variable gain amplifier

The present invention discloses a DC offset canceling circuit applied in a variable gain amplifier. The DC offset canceling circuit comprises a transconductance amplifier and at least one internal capacitor to function as a filter. The input of the transconductance amplifier is electrically connected to the output of the variable gain amplifier, and the output of the transconductance amplifier and the at least one internal capacitor are electrically connected to the input of the variable gain amplifier to form a feedback loop. To cooperate with the function of the DC offset cancelation, the input stage of the variable gain amplifier comprises an auxiliary differential pair.

DC offset cancelling circuit applied in a variable gain amplifier

The present invention is to provide a low voltage fully differential analog-to-digital converter. The converter consists of an input stage including a plurality of pre-amplifier differential input cells for producing pre-amplified signals, a successive processing stage for receiving pre-amplified signals from the input stages, and a decoder for output converted signals according to the signals from the successive processing stage. Each differential input cell includes first and second differential pre-amplifiers, a bias impedance, and an averaging impedance branch. The first and second differential pre-amplifiers include two transistors, respectively, and differentially amplify a set of input signals. One terminal of the bias impedance is connected to a high supplied voltage while the other terminal of the bias impedance is connected to the first and second output terminals through respective pieces of load bearing impedance in order to adjust output voltages of first and second output terminals. Moreover, the averaging impedance branch includes an impedance connecting the second output terminal and the first output terminal of an adjacent differential input cell and another impedance connecting the other end of the bias impedance and the other end of the bias impedance of the adjacent differential input cell.

Low voltage fully differential analog-to-digital converter

This invention deals with the problem of an error voltage in a MOSFET analog switch sample and hold circuit caused by the turn off charge in the MOSFET analog switch. The invention provides a compensating circuit which can be adjusted to exactly compensate for the turn off charge which causes the error so that the error can be reduced to zero or nearly zero. The compensating circuit can be used in both open loop and closed loop sample and hold circuits. The compensating circuit can be used in combination with a Miller feedback circuit for eliminating the error voltage.

Compensating circuit for MOSFET analog switches

Growing community of inventors

Hsinchu, Taiwan

Wei-Chen Shen