Analog Devices,inc.

Wei Che

Lin Li

Tianjiang Li

Seamus Ryan

Niall Daniel O'Connell

Huide Li

Weijun Xu

Hui De Li

Embodiments of the present invention may provide a clock and timing generation scheme for a video signal processor (e.g., a scaler), which enables fast switching between different input video standards without disturbing the output clock or timing. The scheme also may minimize the number of video frames that are dropped or repeated at the output. This may be achieved by locking the video's output timing to the input timing and also by utilizing a frame buffer to remove instantaneous discontinuities caused when an input is changed.

Video processor timing generation

Embodiments of the present invention are directed to an image processing system. The image processing system may comprise a content detection module having an input to receive a sequence of input pixels and configured to generate an adjustable parameter based on detected differences between adjacent pairs of input pixels, and a digital filter having an input for the sequence of input pixels and a control input coupled to an output of the content detection module. The digital filter may adjust filtering coefficients according to the parameter.

Content adaptive scaler based on a farrow structure

A system and a method may include performing a coarse estimation to eliminate at least one direction from a set of edge candidate directions without directly evaluating each direction; performing a fine estimation to select a single direction as corresponding to an edge; and performing a directional interpolation as a function of the single selected direction to generate a pixel value for a pixel being interpolated.

Method and system for efficient de-interlacing

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Beijing, China

Wei Che