Intel Corporation

University of California

Intel Ndtm US LLC

Wei Cao

Krishna Kumar Parat

Richard M Fastow

Xuehong Yu

Narayanan Ramanan

Xin Sun

Hyungseok Kim

Amol Ramesh Joshi

Kaustav Banerjee

Chao-Hui Yeh

Arnab Pal

Amol R Joshi

A hybrid switch and memory cell includes a transistor device that has an atomically-thin semiconductor material channel, source/drain electrodes, and gate dielectric. The cell includes a resistive-random-access-memory having a thin conductive edge and a 2D insulator layer over the thin conductive edge, wherein the 2D insulator layer extends over the semiconductor channel and serves as the gate dielectric in the transistor device.

Hybrid transistor and memory cell

An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.

Method and apparatus to mitigate hot electron read disturbs in 3D nand devices

Method and apparatus to mitigate hot electron read disturbs in 3D NAND devices

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Goleta, CA, United States of America

Wei Cao