Industrial Technology Research Institute

Wei-Bin Yang

Yu-Lung Lo

Kuo-Hsing Cheng

Ting-Sheng Chao

Shu-Chang Kuo

Ting-Sheng Jau

A dynamic floating input D flip-flop (DFIDFF) is provided. The DFIDFF includes a floating input stage, a first string of transistors, and a second string of transistors. At a pre-charge period, the floating input stage transmits the input data to the first string of transistors; the first string of transistors stores the logic status of the input data, and pre-charges its output node to a first level. At an evaluation period, the first string of transistors decides its output node level in accordance with data logic status stored in the first string of transistors; and the second string of transistors decides output level of the D flip-flop in accordance with logic status of the output node of the first string of transistors.

Dynamic floating input D flip-flop

A storage unit capable of retaining data during sleep mode. The storage unit includes a first latch composed of first and second inverters and a second latch composed of the first inverter and a third inverter, in which the first and second inverters have different threshold voltages. The first inverter comprises an input terminal coupled to a write port and an output coupled to a read port. The second inverter comprises an input terminal coupled to the read port and an output terminal coupled to the write port. The third inverter comprises an input terminal coupled to the write port and an output terminal coupled to the read port.

Storage units and register file using the same

A divider is provided. The divider includes a first flip-flop, a flip-flop array, a first NOT gate, a second NOT gate, and a circuit. The first flip-flop can be triggered by a frequency signal. The first NOT gate is coupled between a positive output terminal of the last second flip-flop and the first flip-flop. The second NOT gate is coupled between the positive output terminal of the last second flip-flop and the circuit. The first NOT gate and the second NOT gate are controlled by the mode control signal for enabling. If N is an odd number, the circuit includes a wire, and if N is an even number, the circuit includes a third NOT gate.

Divider

Clock generators capable of generating clocks with different frequency according to a binary code. A voltage controlled oscillation module generates a plurality of first clocks (D&#x2dc;D) with a first frequency (f), in which the first clocks Dand Dhave a fixed phase difference and 1&#x3c;i&#x3c;m. A logic control circuit outputs a set of corresponding clocks arranged in a corresponding sequence according to the first clocks and a binary code. A clock synthesizer generates a second clock with a second frequency (f) according to the set of corresponding clocks, in which f=A/B fA&#x3c;B and A and B are positive integers.

Growing community of inventors

Taichung County, Taiwan

Wei-Bin Yang