Broadcom Corporation

Wee Teck Lee

David Seng Poh Ho

Tian Hwee Teo

Tu Yun

David Ho

Khim Leng Low

Tak Ying Wong

A circuit for protection of a transceiver input includes an input transistor and a first resistor connected between the drain of the input transistor and an input node. A plurality of reverse-biased diodes connected between a supply voltage and the input node. An output node is connected to the source of the input transistor. A first forward-biased diode connected between the power supply and the plurality of reverse-biased transistors. A second forward-biased diode and a second resistor are connected between the first forward biased transistor and the gate of the input transistor. A pre-driver circuit includes first and second transistors forming a differential pair and driven by a differential input voltage. A third transistor is connected between sources of the first and second transistors and ground. First and second resistors are connected to drains of the first and second transistors, respectively. A fourth transistor is connected between a power supply voltage and the first and second resistors. Fifth and a sixth transistors are connected in series between the power supply voltage and the first and second resistors, wherein a node between the fifth and second transistors is connected to a gate of the fourth transistor.

Apparatus and method for over-voltage, under-voltage and over-current stress protection for transceiver input and output circuitry

A differential line driver includes a plurality of driver cells. Control logic outputs positive and negative control signals to the driver cells so as to match a combined output impedance of the driver cells at (Vop, Von). Each driver cell includes an input Vip and an input Vin, an output Vop and an output Von, a first PMOS transistor and a first NMOS transistor having gates driven by the input Vip, and a second PMOS transistor and a second NMOS transistor having gates driven by the input Vin. A source of the first PMOS transistor is connected to a source of the second PMOS transistor. A source of the first NMOS transistor is connected to a source of the second NMOS transistor. First and second resistors are connected in series between the first PMOS transistor and the first NMOS transistor, and connected together at Von. Third and fourth resistors are connected in series between the second PMOS transistor and the second NMOS transistor, and connected together at Vop. A first output switch is driven by a corresponding positive control signal and connected between a supply voltage and the sources of the first and second PMOS transistors. A second output switch driven by a corresponding negative control signal and connected between a ground and the sources of the first and second PMOS transistors.

Series terminated CMOS output driver with impedance calibration

A current mode logic (CML) flip flop includes a first CML latch and a second CML latch. A plurality of pull-up switches are responsive to a reset signal. Outputs of the first and second CML latches are pulled up to a supply voltage through the pull-up switches. The first CML latch includes a first pull-up isolation switch driven by the reset signal for resetting the latch.

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Singapore, Singapore

Wee Teck Lee