Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Singapore Pte. Ltd.

Wee Leng Tan

John Leonard Sudijono

Liang Choo Hsia

Khee Yong Lim

Yong Meng Lee

Wenhe Lin

Chung Woh Lai

Young Way Teh

Hui Peng Koh

Simon Yew-Meng Chooi

Kin Leong Pey

A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.

Spacer-less low-K dielectric processes

An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.

Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS

Spacer-less low-k dielectric processes

An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have an silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.

An example method embodiment forms spacers that create tensile stress on the substrate on both the PFET and NFET regions. We form PFET and NFET gates and form tensile spacers on the PFET and NFET gates. We implant first ions into the tensile PFET spacers to form neutralized stress PFET spacers. The neutralized stress PFET spacers relieve the tensile stress created by the tensile stress spacers on the substrate. This improves device performance.

Composite stress spacer

Methods for forming a high quality nickel silicide film in the fabrication of an integrated circuit are described. A semiconductor substrate is provided having silicon regions to be silicided wherein a native oxide layer forms on the silicon regions. A nickel layer is deposited overlying the silicon regions to be silicided. A titanium layer is deposited overlying the nickel layer. The substrate is annealed whereby titanium atoms from the titanium layer diffuse through the nickel layer and react with the native oxide layer and whereby the nickel is transformed to nickel silicide where it overlies the silicon regions and wherein the nickel not overlying the silicon regions is unreacted. In an alternative method, a titanium nitride layer over the titanium layer traps atmospheric oxygen freeing all of the titanium in the titanium layer to react with the underlying native oxide. The unreacted nickel layer is removed to complete formation of a nickel silicide film in the manufacture of an integrated circuit. In another method, a monolayer of titanium is deposited by atomic layer chemical vapor deposition underlying the nickel layer. The substrate is annealed whereby titanium atoms from the titanium monolayer react with the native oxide layer and whereby the the nickel is transformed to nickel silicide.

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Singapore, Singapore

Wee Leng Tan