Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Singapore Pte. Ltd.

National University of Singapore

Wee Kiong Choi

Lap Chan

Wai Kin Chim

Vivian Ng

Lee Wee Teo

Vincent Ho

Han Guan Chew

Fei Zheng

Cheng Lin Heng

Tze Haw Liew

A method of forming a discrete nanostructured element at one or more predetermined locations on a substrate is presented. The method includes forming a mask member over the substrate. A window is formed in the mask member at each of one or more locations at which it is required to form the nanostructured element thereby to expose a portion of a surface of the substrate. A portion of the substrate exposed by the window at the one or more locations is removed to form one or more recesses in the substrate. The method further includes forming a layer of a nanostructure medium over a surface of the recess and annealing the structure thereby to form the nanostructured element in each of the one or more recesses. The nanostructured element includes a portion of the nanostructure medium and has an external dimension along at least two substantially orthogonal directions of less than substantially 100 nm.

Method of forming a nanostructure

Devices with embedded silicon or germanium nanocrystals, fabricated using ion implantation, exhibit superior data-retention characteristics relative to conventional floating-gate devices. However, the prior art use of ion implantation for their manufacture introduces several problems. These have been overcome by initial use of rapid thermal oxidation to grow a high quality layer of thin tunnel oxide. Chemical vapor deposition is then used to deposit a germanium doped oxide layer. A capping oxide is then deposited following which the structure is rapid thermally annealed to synthesize the germanium nanocrystals.

Process to manufacture nonvolatile MOS memory device

A Flash memory is provided having a trilayer structure of rapid thermal oxide/germanium (Ge) nanocrystals in silicon dioxide (SiO )/sputtered SiO cap with demonstrated via capacitance versus voltage (C-V) measurements having memory hysteresis due to Ge nanocrystals in the middle layer of the trilayer structure. The Ge nanocrystals are synthesized by rapid thermal annealing of a co-sputtered Ge&plus;SiO layer.

Nanocrystal flash memory device and manufacturing method therefor

Growing community of inventors

Singapore, Singapore

Wee Kiong Choi