Intel Corporation

Wee Hoo Cheah

Chun Hung Pang

Kuan Loon Tan

David W Grawrock

Bruce Querbach

Tieyu Zheng

Keshavan K Tiruvallur

Mark B Trobough

Chinna B Prudvi

Vui Yong Liew

Hermann Gartler

Ashok N Kabadi

Samie B Samaan

Keith A Drescher

Jay Joseph Nejedlo

Mukesh Kataria

Lyle E Cool

Russell J Wunderlich

James J Grealish

Brian Meyer

Abhijit Davare

Priyadarsan Patra

William Penner

Ridvan A Sahan

Rahima K Mohammed

Arun R Ramadorai

Kapila B Udawatta

Yuen Tat Lee

John L Baudrexl

Kip C Killpack

Loren James McConnell

Kyle Markley

Christian E Iovin

Sanjay S Salem

Travis K Goff

David C Florey

Evan J Halprin

Jiun Long Foo

Selvakumar Raja Gopal

Neil Dobler

Nagib Z Hakim

Timothy S Storey

Yi Amy Xia

Edwin E Parks

Padmakumar Gopal

An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

Test, validation, and debug architecture

In some embodiments, a serial bus interface circuit includes at least two serial ports, a memory to store a relationship between serial bus addresses and the at least two serial ports, and a controller to control access to the at least two serial ports. The controller may be configured to receive an access request for a serial bus address, determine a first port of the at least two serial ports corresponding to the serial bus address using the relationships stored in the memory, and disable a second port of the at least two serial ports. Other embodiments are disclosed and claimed.

Multiple serial port controller

Method and apparatus to reduce serial bus transmission power

Growing community of inventors

Bayan Lepas, Malaysia

Wee Hoo Cheah