Infineon Technologies Ag

Wee Aun Jason Lim

Chooi Mei Chong

Liu Chen

Sanjay Kumar Murugan

Chee Voon Tan

Wee Boon Tay

Paul Armand Asentista Calo

Edward Myers

Chee Chiew Chong

Ying Pok Sam

Ting Soon Chin

A molded semiconductor package arrangement may comprise a die pad configured to support a semiconductor; a set of leads; and a mold structure that is formed to enclose the semiconductor and the die pad within the mold structure. The set of leads and the die pad may be formed from a same piece of conductive material. An electrical contact plane of the set of leads may be offset from a bottom surface of the die pad. The mold structure may include a molded standoff that is beneath the die pad. A bottom surface of the molded standoff may extend below the electrical contact plane of the set of leads by a threshold distance that corresponds to a thickness of the molded standoff.

Topside-cooled semiconductor package with molded standoff

A power semiconductor package includes a power semiconductor chip, an electrical connector arranged at a first side of the power semiconductor chip and having a first surface that is coupled to a power electrode of the power semiconductor chip, an encapsulation body at least partially encapsulating the power semiconductor chip and the electrical connector, and an electrical insulation layer arranged at a second surface of the electrical connector opposite the first surface, wherein parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.

Power semiconductor package and method for fabricating a power semiconductor package

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Melaka, Malaysia

Wee Aun Jason Lim