Altera Corporation

Wayne Yeung

Chiakang Sung

Joseph Huang

Bonnie I Wang

Khai Nguyen

Xiaobao Wang

In Whan Kim

Richard G Cliff

Bruce B Pedersen

Christopher F Lane

Myron Wai Wong

Giles V Powell

Im Whan Kim

A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit. In an implementation, the programmable phase shift circuitry is implemented using two programmable counters.

Voltage, temperature, and process independent programmable phase shift for PLL

A programmable logic device is equipped for low voltage differential signaling ('LVDS') by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

Programmable logic integrated circuit devices with low voltage differential signaling capabilities

A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.

Programmable phase shift circuitry

Interconnection block arrangements for selectively interconnecting logic on a programmable logic device is provided. Programmable logic connectors within the interconnection blocks may be programmed to route signals between the various conductors on the device and to route signals from various logic regions on the device to the various conductors. The interconnection blocks are arranged to optimize the use of metallization resources and to increase interconnectivity and logic density.

Efficient arrangement of interconnection resources on programmable logic devices

A phase frequency detector (PFD) circuit ( ) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals ( ). The phase frequency detector has more than three states. The PFD circuit may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. The PFD circuitry will allow for a fast lock acquisition time, even when there is a relatively wide frequency range between the two clock signals.

Fast locking phase frequency detector

A programmable logic device is equipped for low voltage differential signaling (&ldquo;LVDS&rdquo;) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.

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Wayne Yeung