Sun Microsystems, Inc.

Nvidia Corporation

Mips Tech Limited

Wayne Yamamoto

Sudarshan Kadambi

Vijay Balakrishnan

Emmett Michael Kilgariff

Adam R Talcott

Brian Kelleher

Daniel Lawrence Leibholz

Harit Modi

Christopher A Gomez

Techniques for executing a load instruction in a processor are described. In one example, load instructions which are detected to have an offset (or displacement) of zero are sent directly to a data cache, bypassing the address generation stage thereby reducing pipeline length. Load instructions having a nonzero offset can be executed in an address generation stage as is conventional. To avoid conflicts between a current load instruction with zero offset and a previous load instruction with nonzero offset, the current instruction can be rescheduled or sent through a separate dedicated load pipe. An alternative technique permits a load instruction with zero offset to be issued one cycle earlier than it would need to be if it had a nonzero offset, thus reducing load latency.

Execution of load instructions in a processor

Embodiments of the present technology are directed toward techniques for balancing memory accesses to different memory types.

Techniques for balancing accesses to memory having different memory types

One embodiment of the present invention provides a system for predicting hot spots in a cache memory. Upon receiving a memory operation at the cache, the system determines a target location within the cache for the memory operation. Once the target location is determined, the system increments a counter associated with the target location. If the counter reaches a pre-determined threshold value, the system generates a signal indicating that the target location is a hot spot in the cache memory.

Method and apparatus for predicting hot spots in cache memories

A microprocessor includes multiple register files. In a single thread mode, the microprocessor allows a single thread to have access to multiple ones of the register files. In a multi-thread mode, each thread has access to respective ones of the register files. In the multi-thread mode, multiple threads are simultaneously executing. Circuitry and hardware are provided to facilitate the respective modes and to facilitate transitions between the modes.

MICROPROCESSOR AND METHOD FOR GIVING EACH THREAD EXCLUSIVE ACCESS TO ONE REGISTER FILE IN A MULTI-THREADING MODE AND FOR GIVING AN ACTIVE THREAD ACCESS TO MULTIPLE REGISTER FILES IN A SINGLE THREAD MODE

One embodiment of the present invention provides a system that uses a hot spot cache to alleviate the performance problems caused by hot spots in cache memories, wherein the hot spot cache stores lines that are evicted from hot spots in the cache. Upon receiving a memory operation at the cache, the system performs a lookup for the memory operation in both the cache and the hot spot cache in parallel. If the memory operation is a read operation that causes a miss in the cache and a hit in the hot spot cache, the system reads a data line for the read operation from the hot spot cache, writes the data line to the cache, performs the read operation on the data line in the cache, and then evicts the data line from the hot spot cache.

Method and apparatus for reducing the effects of hot spots in cache memories

One embodiment of the present invention provides a system that reduces the time required to access registers from a register file within a processor. During operation, the system receives an instruction to be executed, wherein the instruction identifies at least one operand to be accessed from the register file. Next, the system looks up the operands in a register pane, wherein the register pane is smaller and faster than the register file and contains copies of a subset of registers from the register file. If the lookup is successful, the system retrieves the operands from the register pane to execute the instruction. Otherwise, if the lookup is not successful, the system retrieves the operands from the register file, and stores the operands into the register pane. This triggers the system to reissue the instruction to be executed again, so that the re-issued instruction retrieves the operands from the register pane.

Method and apparatus for reducing register file access times in pipelined processors

A method of optimizing speculative address load processing by a microprocessor includes identifying a speculative load, marking the speculative load, determining whether a miss occurs for the speculative load, and preventing use of the marked speculative load by the microprocessor if a miss occurs. A method of optimizing speculative address load processing by a microprocessor includes identifying a speculative load, marking the speculative load, inserting the marked speculative load into a load miss queue, determining whether a miss occurs for the speculative load, and preventing the load miss queue from committing the marked speculative load to cache if a miss occurs.

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Saratoga, CA, United States of America

Wayne Yamamoto