Hewlett-packard Company

Mcdata Corporation

Wayne Wu

Dwayne R Bennett

Clifford S Yeung

A system and method for inserting intermix frames into a continuous stream of class 1 frames. A bypass bus, in conjunction with a buffer, are provided within a fiber optic switch element, to route intermix data frame through the switch that is concurrently transmitting class 1 data. A channel module, which is disposed between a switch module and a plurality of fiber optic channels, comprises a port intelligence system and a memory interface system. The port intelligence system is responsible for transmitting and receiving data from the fiber optic channels in accordance with a predetermined protocol, preferably Fibre Channel. The memory interface system comprises a receive memory unit, a transmit memory unit and memory control logic. When an intermix frame is to be passed through the switch, the intermix frame is passed to the buffer concurrently while class 1 data transfer occurs via the bypass bus. After the intermix frame has been completely written into the buffer, the memory control logic waits to detect a tag indicative of a break in the class 1 data transfer. The control logic will then switch the MUX and cause the buffer to commence writing the intermix frame to the port intelligence system for transfer to a predetermined fiber optic channel.

Bypass switching and messaging mechanism for providing intermix data

A method and apparatus for high speed decoding of a 20 bit wide data into 16-bit wide data in which the first ten bits and the lower ten bits are decoded simultaneously to ensure complete decoding and where the decoding of the second ten bits is dependent upon the running disparity of the first ten bits, the second ten bits are decoded twice, one assuming the decoded first ten bits will have a positive running disparity, and a second time assuming that the decoded first ten bits will have a negative running disparity.

Method and apparatus for transmission code decoding and encoding

A system and method for inserting intermix frames into a continuous stream of class 1 frames. A bypass bus, in conjunction with a first-in-first-out (FIFO) buffer, are provided within a fiber optic switch element, to route intermix data frame through the switch that is concurrently transmitting class 1 data. A channel module, which is disposed between a switch module and a plurality of fiber optic channels, comprises a port intelligence system and a memory interface system. The port intelligence system is responsible for transmitting and receiving data from the fiber optic channels in accordance with a predetermined protocol, preferably Fibre Channel. The memory interface system comprises a receive memory unit, a transmit memory unit and memory control logic. When an intermix frame is to be passed through the switch, the intermix frame is passed to a FIFO concurrently while class 1 data transfer occurs via the bypass bus. After the intermix frame has been completely written into the FIFO, the memory control logic waits to detect a tag indicative of a break in the class 1 data transfer. The control logic will then switch the MUX and cause the FIFO to commence writing the intermix frame to the port intelligence system for transfer to a predetermined fiber optic channel.

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Rexdale, Canada

Wayne Wu