Actel Corporation, Inc.

Other

Wayne W Wong

William C Plants

Arunangshu Kundu

James Dean Joseph

Nikhil Mazumder

Shin-Nan Sun

A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.

Delay locked loop for an FPGA architecture

A system for encrypting and decrypting data in a data stream for programming a Field Programmable Gate Array (FPGA). The system allows for an enable bit to be set for a gap in the data stream and the data is then encrypted from the beginning of the gap. A gap being bits in said data stream that correspond to unprogrammed addresses of a memory in the field programmable gate array. The data is then decrypted by the FPGA when the bit stream is received and an enable bit is detected in a gap of the data stream.

Encryption for a stream file in an FPGA integrated circuit

The present invention comprises apparatus and a method for simultaneously programming multiple antifuses in a multiple tile field programmable gate array (FPGA). The invention comprises an FPGA having a plurality of logic modules with programmable elements. The logic modules are partitioned into a plurality of individually programmable groups and an isolation device may be coupled between the individually programmable groups of logic modules such that each of the programmable elements in each of the plurality of individually programmable logic modules may be programmed concurrently.

Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA

Delay locked loop for and FPGA architecture

Growing community of inventors

Sunnyvale, CA, United States of America

Wayne W Wong