Freescale Semiconductor,inc.

Motorola Corporation

Nxp Usa, Inc.

Freescale Semiconductors Inc.

Wayne R Burger

Xiaowei Ren

Robert A Pryor

Christopher Paul Dragon

Colin Kerr

Mark A Bennett

Paul W Sanders

Thuy B Dao

Michael F Petras

Joel E Keys

Jeffrey Kevin Jones

Margaret A Szymanowski

David Cobb Burdeaux

Daniel J Lamey

Michele Lynn Miera

Zihao M Gao

David K Lovelace

Philippe Renaud

Julio C Costa

Hernan A Rueda

Yee-Chaung See

David Q Ngo

Natalino Camilleri

Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., &#x2267;100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC previously unobtainable.

Monolithic microwave integrated circuits

A semiconductor device with a current terminal region located in a device active area of a substrate of the device. A guard region is located in a termination area of the device. A plurality of floating field plates are located in the termination area and are ohmically coupled to the guard region. The floating field plates and guard region act in some embodiments to 'smooth' the electrical field distribution along the termination area.

Semiconductor device with floating field plates

A device includes a semiconductor substrate having a surface with a trench, first and second conduction terminals supported by the semiconductor substrate, a control electrode supported by the semiconductor substrate between the first and second conduction terminals and configured to control flow of charge carriers during operation between the first and second conduction terminals, and a Faraday shield supported by the semiconductor substrate and disposed between the control electrode and the second conduction terminal. At least a portion of the Faraday shield is disposed in the trench.

Trenched Faraday shielding

Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., &#x2267;100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face () of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC previously unobtainable.

Methods of making a monolithic microwave integrated circuit

Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., &#x2267;100 Ohm-cm) semiconductor substrates () and lower resistance inductors (') for the IC (). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors () and interconnections (--&#x2033;) overlying the substrate (). The active transistor(s) (&#x2032;) are formed in the substrate () proximate the front face (). Planar capacitors (&#x2032;) are also formed over the front face () of the substrate (). Various terminals (------&#x2032;, etc.) of the transistor(s) (&#x2032;), capacitor(s) (&#x2032;) and inductor(s) (&#x2032;) are coupled to a ground plane () on the rear face () of the substrate () using through-substrate-vias (&#x2032;) to minimize parasitic resistance. Parasitic resistance associated with the planar inductors (&#x2032;) and heavy current carrying conductors (-&#x2032;) is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC () previously unobtainable.

Monolithic microwave integrated circuit

Embodiments of integrated passive devices (e.g., metal insulator metal, or MIM, capacitors) and methods of their formation include depositing a composite electrode over a semiconductor substrate (e.g., on a dielectric layer above the substrate surface), and depositing an insulator layer over the composite electrode. The composite electrode includes an underlying electrode and an overlying electrode deposited on a top surface of the underlying electrode. The underlying electrode is formed from a first conductive material (e.g., AlCuW), and the overlying electrode is formed from a second, different conductive material (e.g., AlCu). The top surface of the underlying electrode may have a relatively rough surface morphology, and the top surface of the overlying electrode may have a relatively smooth surface morphology. For high frequency, high power applications, both the composite electrode and the insulator layer may be thicker than in some conventional integrated passive devices.

Integrated circuits including integrated passive devices and methods of manufacture thereof

Electronic elements having an active device region and integrated passive device (IPD) region on a common substrate preferably include a composite dielectric region in the IPD region underlying the IPD to reduce electro-magnetic (E-M) coupling to the substrate. Mechanical stress created by plain dielectric regions and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions in the composite dielectric region of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material in the composite dielectric region. For silicon substrates, non-single crystal silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material.

Low loss substrate for integrated passive devices

Electronic elements having an active device region and bonding pad (BP) region on a common substrate desirably include a dielectric region underlying the BP to reduce the parasitic impedance of the BP and its interconnection as the electronic elements are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region having electrically isolated inclusions of a thermal expansion coefficient (TEC) less than that of the dielectric material in which they are embedded and/or closer to the substrate TEC. For silicon substrates, poly or amorphous silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material.

Electronic elements and devices with trench under bond pad feature

Electronic elements (&#x2033;) having an active device region () and integrated passive device (IPD) region () on a common substrate () preferably include a composite dielectric region (&#x2033;) in the IPD region underlying the IPD () to reduce electromagnetic (E-M) () coupling to the substrate (). Mechanical stress created by plain dielectric regions (') and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions (&#x2033;) in the composite dielectric region (&#x2033;) of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material (&#x2033;) in the composite dielectric region (&#x2033;). For silicon substrates (), non-single crystal silicon is suitable for the inclusions (&#x2033;) and silicon oxide for the dielectric material (&#x2033;). The inclusions (&#x2033;) preferably have a blade-like shape separated by and enclosed within the dielectric material (&#x2033;).

Electronic elements (&#x2033;) having an active device region () and bonding pad (BP) region () on a common substrate () desirably include a dielectric region underlying the BP () to reduce the parasitic impedance of the BP () and its interconnection () as the electronic elements (&#x2033;) are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions (') can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region (&#x2033;) having electrically isolated inclusions (&#x2032;) of a thermal expansion coefficient (TEC) less than that of the dielectric material (&#x2033;) in which they are embedded and/or closer to the substrate () TEC. For silicon substrates (), poly or amorphous silicon is suitable for the inclusions (&#x2033;) and silicon oxide for the dielectric material (&#x2033;). The inclusions (&#x2033;) preferably have a blade-like shape separated by and enclosed within the dielectric material (&#x2033;).

Methods for forming an RF device with trench under bond pad feature

An RF power transistor with a metal design () comprises a drain pad () and a plurality of metal drain fingers () extending from the drain pad, wherein at least one metal drain finger comprises one or more sections of metal (-----), each section of metal including of one or more branch (-------) of metal having a metal width maintained within a bamboo regime.

RF power transistor device with metal electromigration design and method thereof

A semiconductor device ( ) having a gate ( ), a source ( ), and a drain ( ) with a gate bus ( ) and first ground shield ( ) patterned from a first metal layer and a second ground shield ( ) patterned from a second metal layer. The first ground shield ( ) and the second ground shield ( ) lower the capacitance of device ( ) making it suitable for high frequency applications and housing in a plastic package.

High frequency semiconductor device and method of manufacture

A high frequency power FET device (22) is integrated with passive components (23,24,26,28,31), an electro-static discharge (ESD) device (27,127,227), and/or a logic structure (29) on a semiconductor body (13) to form a monolithic high frequency integrated circuit structure (10). The high frequency power FET device (22) includes a grounded source configuration. The logic structure (29) utilizes the high frequency power FET structure in a grounded source configuration as one device in a CMOS implementation.

Monolithic high frequency integrated circuit structure having a grounded

A lateral bipolar transistor (10) includes a retrograde doping profile (21) that is formed within a substrate (11) to form the transistor's (10) collector region (14). A base region (16) that includes an inactive base area and an active base area (17) is formed in the collector region (14). An emitter (18) is formed within the active base area (17) wherein current (22) flows through the emitter (18) through the active base area (17) and through the collector region (14). The base region, the emitter, and a collector contact region are all formed by driving dopants from an overlying polysilicon layer.

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Phoenix, AZ, United States of America

Wayne R Burger