Motorola Corporation

Wayne P Shepherd

James S Irwin

Darrell Eugene Davis

Joseph P Heck

Frederick L Martin

Jose I Suarez

Enrique Ferrer

Ralph T Enderby

Wan F Tay

A digital frequency synthesizer circuit with spur compensation includes a demodulator circuit (118) for demodulating the output signal (116) of the synthesizer's accumulator (108). Demodulator (118) also inverts the signal, and provides an inverted demodulated output signal (142) which is then coupled to the synthesizer clock (124) after passing through a gain stage (122) in order to modulate the synthesizer clock (124) with a compensation signal (146). The compensated clock signal (140) is then sent to accumulator (108) in order to substantially cancel out any jitter in the accumulator's output signal (116). The modulation signal (MOD IN) which is digitally applied to accumulator (108) is applied in analog fashion to the gain stage (122) in order to prevent the desired modulation signal (MOD IN) from being canceled in the output signal (116).

Compensated digital frequency synthesizer

A voltage level shifting circuit (100) comprises an input port (160) and output terminal (162). The voltage level shifting circuit (100) further comprises a voltage translation circuit which generates first and second voltage levels, both of which are related to the input reference voltage and which both vary with variations in the input voltage. A control circuit (158) controls which of the two voltage levels produced by the voltage translation circuit is presented at output terminal (162), depending on the voltage level at the control circuit input port (168).

Variable level translator

A synthesizer circuit with spur compensation utilizes fractional division in the synthesizer loop. The fractional divider includes means for compensating the spurs when the fractional numerator N=0. The synthesizer includes means for selecting a reference divisor R such that a non zero value of fractional numerator is produced and such that the generated spurs fall below the side band noise limits of the synthesizer's voltage controlled oscillator.

Fractional-N synthesizer having modulation spur compensation

A frequency synthesizer (10) for providing a modulated output signal (fo) includes a reference frequency signal (fr) and a voltage controlled oscillator (14). For dividing the frequency of the output signal from the voltage controlled oscillator (14) by a divisor, a programmable divider (16) is coupled to the output of the voltage controlled oscillator (14). To produce a phase-locked loop in which the frequency of the output signal from the voltage controlled oscillator (14) is equal to the frequency of the reference frequency (fr) signal multiplied by the divisor, a phase detector (12 ) having a first input coupled to the reference frequency signal (fr), a second input coupled to the output of the programmable divider (16), and an output coupled to the input of the voltage controlled oscillator (14) is also provided. A first integrator (24) for integrating a modulating signal provides an integrated signal and a first control signal. Similarly, a second integrator (25) coupled to the first integrator (24) for integrating the integrated signal provides a second control signal. A differentiator ( 36, 42 and 48) coupled to the second integrator (25) differentiates the second control signal to provide a third control signal. Finally, a processor (41 and 43) coupled to the first integrator (24), the second integrator (25) and the differentiator (36, 42 and 48) processes the first, second, and third control signals and a divider modulus code (M). The processor (41 and 43) coupled to the programmable divider modifies the divider modulus code (M) in response to the modulating signal (9) to provide the divisor, whereby the frequency of the output signal from the voltage controlled oscillator (14) is modulated by the modulating signal (9).

Frequency synthesizer with FM modulation

A phase locked loop (100) with a sample and hold phase detector (106) with adjustable gain. A switching circuit adjusts the slew rate of the phase detector by either introducing additional ramp capacitance (122) in the phase detector or by increasing the current for charging the ramp capacitor (116).

Phase locked loop

A frequency synthesizer for providing a modulated output signal includes a phase comparator, a loop filter, and a voltage controlled oscillator (VCO). The phase comparator receives a reference input signal and a signal related to the VCO output, and generates a control current. A modulation circuit receives a modulation signal and provides both a modulation current and a modulation voltage. The modulation current is summed with the control current at one input of the loop filter, while the modulation voltage is applied to a second input of the loop filter. The VCO is controlled by the output of the loop filter to produce the modulated output signal.

Loop filter modulated synthesizer

A variable capacitance circuit includes a varactor having an anode side and a cathode side. A first variable bias voltage is applied to one of the sides and one of a plurality of voltages is applied as a second bias voltage to the other side for controlling the capacitance of the varactor. A voltage multiplier circuit connected to a voltage divider network is used for supplying the plurality of voltages. A decoder is responsive to input signals for selecting and applying one of the multiple voltage outputs. The variable capacitance circuit is used in a voltage controlled oscillator of a frequency synthesizer for providing extended frequency range.

Varactor tuning circuit having plural selectable bias voltages

A frequency synthesizer is provided including a reference frequency generator coupled to one input of a phase detector. The output of the phase detector is coupled via a pair of alternatingly connected filters through a voltage controlled oscillator and a divider circuit to the remaining input of the phase detector to form a phase locked loop. The first filter of the pair is designated for operation on a main channel frequency while the remaining filter is designated for operation on a priority channel frequency. The capacitive elements of each respective filter remain fully charged up for operation on their respective frequencies and thus when such filters are alternately switched between to change frequency from the main channel to the priority channel, the capacitive elements need not be charged to new levels to accommodate such frequency change. Thus, switching between a main channel and a priority channel is accomplished in a minimal amount of time with a significant reduction in frequency synthesizer energy requirements.

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Sunrise, FL, United States of America

Wayne P Shepherd