Macom Technology Solutions Holdings, Inc.

The Whitaker Corporation

M/a -com, Inc.

Triquint Semiconductor Corporation

Tyco Electronics Corporation

Wayne Mack Struble

Timothy Edward Boles

Gabriel R Cueva

Allen W Hanson

Eoin Carey

Shane M Collins

Ronan G Brady

John Stephen Atherton

Shamit Som

Jason Matthew Barrett

Norbert Andrew Schmitz

Nishant R Yamujala

Michael T Murphy

Richard John Giacchino

Chuanxin Lian

Kevin Harrington

Brian Khabbaz

John Claassen Roberts

Kohei Fujii

Paul John Schwab

Walter H Nagy

Douglas Carlson

Yan Zhang

Alan Linde Noll

Haoyang Yu

Stephane Beaussart

An example field effect transistor includes a substrate, a first source metal over the substrate, a second source metal over the substrate, and a drain metal positioned between the first source metal and the second source metal over a channel of the field effect transistor. The drain metal includes a drain metal body having a notched region between the first source metal and the second source metal over the channel, and the notched region defines a first projecting portion and a second projecting portion of the drain metal body. In one aspect, the first projecting portion and the second projecting portion are positioned on respective sides of the notched region. The notched region is a triangular-shaped notched region in one example.

Layout techniques and optimization for power transistors

A power amplifier has an amplifier cell with an input terminal receiving an input signal and an output terminal providing an output signal. A bias network is coupled to the output terminal of the amplifier cell to provide a bias signal to the amplifier cell. A shutdown circuit is coupled to the bias network to disable the bias network in response to the input signal. The shutdown circuit has a transistor with a first conduction terminal coupled to the bias network, a second conduction terminal coupled to a power supply terminal. The shutdown circuit further has a first resistor with a first terminal coupled to the input terminal, and a second resistor with a first terminal coupled to a second terminal of the first resistor at a node, and a second terminal coupled to the power supply terminal. The control terminal of the transistor is coupled to the node.

Circuit and method of shutdown for bias network in high voltage amplifier

Semiconductor structures with reduced parasitic capacitance between interconnects and ground, for example, are described. An example method for making a semiconductor structure includes forming a trench in an interconnect area of a substrate between first and second device areas in the semiconductor structure, forming a low dielectric constant material region in the trench, forming a III-nitride material layer over the substrate and over the low dielectric constant material region in the trench, forming a first device in the III-nitride material layer in the first device area, forming a second device in the III-nitride material layer in the second device area, and forming an interconnect over the low dielectric constant material region, the interconnect comprising a continuous conductive metal interconnect from the first device area, over the low dielectric constant material region, and to the second device area.

Parasitic capacitance reduction in GaN-on-silicon devices

Extrinsic structures formed outside the active regions of active devices can influence aging characteristics and performance of the active devices. An example integrated device including such an extrinsic structure includes an active region of a semiconductor device in a plurality of layers of semiconductor materials over a substrate, an isolation region in at least one of the layers of semiconductor materials, the isolation region extending around the semiconductor device in an area outside of the active region, an insulating layer over at least a portion of the active region and over at least a portion of the isolation region, a via in the isolation region and outside the active region, the via extending through the insulating layer and down to a conduction layer among the layers of semiconductor materials in the isolation region, and an interconnect within the via and directly on the conduction layer in the isolation region.

Extrinsic field termination structures for improving reliability of high-voltage, high-power active devices

An electrode structure for a device, such as a GaN or AlGaN device is described. In one example, a method to form the structure includes providing a substrate including gallium nitride material, forming an insulating layer over a surface of the substrate, forming an opening in the insulating layer to expose a surface region of the substrate, depositing a barrier metal layer over the insulating layer and onto the surface region of the substrate through the opening, and depositing a conducting metal layer over the barrier metal layer. In one case, the barrier metal layer includes a layer of tungsten nitride. The layer of tungsten nitride is deposited over the insulating layer and onto the surface region of the substrate using atomic layer deposition.

Atomic layer deposition of barrier metal layer for electrode of gallium nitride material device

Various aspects of integrated amplifiers, layouts for the integrated amplifiers, and packaged arrangements of the amplifiers are described. In one example, an amplifier includes an amplifier cell, and a biasing network coupled to the common gate transistor in the amplifier cell. The amplifier cell includes a common source transistor and a common gate transistor in a cascode arrangement, where at least one of the common source transistor and the common gate transistor comprises a field plate. Among other advantages, the amplifiers described herein can be biased with relatively high voltages and still operate like a single a common source transistor, without sacrificing reliability, performance, or requiring additional off-chip components, such as biasing networks of resistors and inductors.

High voltage stacked transistor amplifier

A method of manufacturing an electrode structure for a device, such as a GaN or AlGaN device is described. In one example, the method includes providing a substrate () of GaN or AlGaN with a surface region of the GaN or AlGaN exposed through an opening () in a layer of silicon nitride () formed on the substrate. The method further includes depositing layers of W (), in one example, or Ni () and W (), in another example, on the substrate and the layer of silicon nitride using reactive evaporation and photoresist layers () having an undercut profile for liftoff. The method further includes removing the photoresist layers having the undercut profile, and depositing layers of WN () and Al over the underlying layers of W or Ni and W by sputtering.

Gate metal formation on gallium nitride or aluminum gallium nitride

Extrinsic structures formed outside the active regions of active devices can influence aging characteristics and performance of the active devices. An example integrated device including such an intrinsic structure includes a semiconductor device having an active region in a conduction layer, an isolation region in the conduction layer, an insulating layer formed over at least a portion of the active region and over at least a portion of the isolation region, a via outside the active region, and a conductive interconnect. The isolation region extends around the semiconductor device in an area outside the active region. The via extends through the insulating layer and down to the isolation region in the conduction layer, and the conductive interconnect is formed directly on the isolation region in the conduction layer.

Semiconductor structures and devices in III-nitride materials are described herein, including material structures comprising III-nitride material regions (e.g., gallium nitride material regions). In certain cases, the material structures comprise substrates having relatively high electrical conductivities. In other cases, the material structures comprise substrates having relatively high resistivities. Certain embodiments include one or more features that reduce the degree to which thermal runaway occurs, which can enhance device performance including at elevated flange temperatures. Some embodiments include one or more features that reduce the degree of capacitive coupling exhibited during operation. For example, in some embodiments, relatively thick III-nitride material regions and/or relatively small ohmic contacts are employed.

Reduced interfacial area III-nitride material semiconductor structures

Various embodiments are disclosed for improved and structurally optimized transistors, such as RF power amplifier transistors. A transistor may include a drain metal portion raised from a surface of a substrate, a drain metal having a notched region, a gate manifold body with angled gate tabs extending from the gate manifold, and/or a source-connected shielding. The transistor may include a high-electron-mobility transistor (HEMT), a gallium nitride (GaN)-on-silicon transistor, a GaN-on-silicon-carbide transistor, or other type of transistor.

Semiconductor structures with reduced parasitic capacitance between interconnects and ground, for example, are described. In one case, a semiconductor structure includes a substrate and a low dielectric constant material region in the substrate. The low dielectric constant material region is positioned between a first device area in the semiconductor structure and a second device area in the semiconductor structure. The semiconductor structure also includes a III-nitride material layer over the substrate. The III-nitride material layer extends over the substrate in the first device area, over the low dielectric constant material region, and over the substrate in the second device area. The semiconductor structure can also include a first device formed in the III-nitride material layer in the first device area, a second device in the III-nitride material layer in the second device area, and an interconnect formed over the low dielectric constant material region. The interconnect can provide a continuous conductive path of metal from the first device area, over the low dielectric constant material region, and to the second device area.

Parasitic capacitance reduction in GaN devices

Apparatus and methods relating to heterolithic microwave integrated circuits HMICs are described. An HMIC can include different semiconductor devices formed from different semiconductor systems in different regions of a same substrate. An HMIC can also include bulk regions of low-loss electrically-insulating material extending through the substrate and located between the different semiconductor regions. Passive RF circuit elements can be formed on the low-loss electrically-insulating material.

Heterolithic integrated circuits including integrated devices formed on semiconductor materials of different elemental composition

A number of integrated circuits and methods of manufacturing the integrated circuits are described. An integrated circuit can include different semiconductor devices formed from different semiconductor systems in different regions over the same substrate. The integrated circuit can also include bulk regions of low-loss electrically-insulating material extending through the substrate and located between the different semiconductor regions. Passive RF circuit elements can be formed on the low-loss electrically-insulating material.

Heterolithic microwave integrated circuits including gallium-nitride devices on intrinsic semiconductor

Various integrated circuits formed using gallium nitride and other materials are described. In one example, an integrated circuit includes a first integrated device formed over a first semiconductor structure in a first region of the integrated circuit, a second integrated device formed over a second semiconductor structure in a second region of the integrated circuit, and a passive component formed over a third region of the integrated circuit, between the first region and the second region. The third region comprises an insulating material, which can be glass in some cases. Further, the passive component can be formed over the glass in the third region. The integrated circuit is designed to avoid electromagnetic coupling between the passive component, during operation of the integrated circuit, and interfacial parasitic conductive layers existing in the first and second semiconductor structures, to improve performance.

Microwave integrated circuits including gallium-nitride devices on silicon

Examples of integrated semiconductor devices are described. In one example, an integrated device includes first and second transistors formed on a substrate, where the transistors share a terminal metal feature to reduce a size of the integrated device. The terminal metal feature can include a shared source electrode metalization, for example, although other electrode metalizations can be shared. In other aspects, a first width of a gate of the first transistor can be greater than a second width of a gate of the second transistor, and the shared metalization can taper from the first width to the second width. The integrated device can also include a metal ground plane on a backside of the substrate, and the terminal metal feature can also include an in-source via for the shared source electrode metalization. The in-source via can electrically couple the shared source electrode metalization to the metal ground plane.

Growing community of inventors

Franklin, MA, United States of America

Wayne Mack Struble