Motorola Corporation

Freescale Semiconductor,inc.

Wayne M Paulson

David W Hughes

Michael P Woo

Thomas C Mele

Bich-Yen Nguyen

Ramachandran Muralidhar

Ted R White

Robert F Steimle

Rajesh A Rao

Bruce E White

Ronald N Legge

Bikas Maiti

Stanley Michael Filipiak

Erwin J Prinz

Syd R Wilson

Frank K Baker

Bernard J Roman

Gordon Tam

Sergio A Ajuria

Wayne J Ray

Charles J Varker

Jung-Hui Lin

T P Ong

Gong Chen

Robert Dwayne Colclasure, Jr

Jon Dahm

James Heddleson

A process of forming a device with nanoclusters. The process includes forming nanoclusters (e.g. silicon nanocrystals) and forming an oxidation barrier layer over the nanoclusters to inhibit oxidizing agents from oxidizing the nanoclusters during a subsequent formation of a dielectric of the device. At least a portion of the oxidation barrier layer is removed after the formation of the dielectric. In one example, the device is a memory wherein the nanoclusters are utilized as charge storage locations for charge storage transistors of the memory. In this example, the oxidation barrier layer protects the nanoclusters from oxidizing agents due to the formation of gate dielectric for high voltage transistors of the memory.

Semiconductor device with nanoclusters

A multi-level registration control system for a photolithography process includes a photolithography device that prints first, second and third layers on a wafer. A first overlay mark defines overlay errors in a first direction between the first and third layer. The first overlay mark also defines overlay errors between the second and third layers. An overlay measurement device measures the overlay errors and generates an overlay signal. A feedback controller is connected to the overlay measurement device and the photolithography device. The feedback controller receives the overlay error signal and generates and transmits an alignment correction signal to the photolithography device. The first overlay mark is a box-in-box overlay mark or a frame-in-frame overlay mark. By providing a single overlay mark to align three layers, the multi-layer overlay control system reduces scribe grid area and saves useful silicone surface area.

Multi-layer registration control for photolithography processes

Antireflective layers (54, 86, and 109) have been developed that have discrete portions (541, 542, 861, 862, 863, 1091, and 1092). The discrete portions (541, 542, 861, 862, 863, 1091, and 1092) allow the antireflective layers (54, 86, and 109) to be used in many instances where using a single layer of uniform composition would be difficult or impossible. Alternatively, a single antireflective layer with a continuously graded composition can be used.

Process for forming a semiconductor device with an antireflective layer

A method for form an integrated circuit device begins by growing a tunnel oxide (22). The tunnel oxide is exposed to a nitrogen containing ambient whereby nitrogen is incorporated at atomic locations at the interface between the tunnel oxide (22) and a substrate (11). This tunnel oxide and nitrogen exposure is performed for all of a floating gate active area (12), a high voltage active area (14) and a logic gate active area (16). A floating gate electrode (24) and interpoly dielectric regions (26 through 30) are then formed in the floating gate region (12). The tunnel oxide (22) is etched from the active areas (14 and 16) whereby nitrogen contamination (32) may remain. An optional sacrificial oxidation and a low temperature 830.degree. C. wet oxidation process utilizing HCL, H2 and O2 is then used to grow a high voltage gate dielectric (34) which has been shown to improve charge to breakdown characteristics by a factor of 1,000. After the formation of the high voltage gate oxide (34), a lower voltage logic gate oxide (36) is then formed.

Method for forming a high voltage gate dielectric for use in integrated

A stack of oxide (16) and silicon nitride (18) is grown/deposited over a patterned polysilicon line, which typically acts as a bottom capacitor plate. A thin layer of amorphous or polycrystalline silicon (20) is deposited over the blanket silicon nitride film. The thickness of the deposited silicon layer must be optimized according to the final amount of oxide desired over the silicon nitride, which will be roughly twice the thickness of the deposited silicon film. The oxide/nitride/silicon stack is then patterned and etched, stopping either at or underneath the bottom oxide. Any subsequent cleaning in potentially oxide-etching chemistries (including HF) is done with the protective silicon deposit on top of the silicon nitride. The entire structure is then thermally oxidized, transforming the deposited silicon into silicon oxide (30). Where the structure has been cleared down to the substrate by etching, a second gate oxide is simultaneously formed.

Method for forming concurrent top oxides using reoxidized silicon in an

The disclosed invention is a method for fabricating a multi-layer semiconductor device using selective planarization. In accordance with one embodiment of the invention, conductive members are formed on a substrate and a first insulating layer is deposited onto the substrate and the conductive members. A second insulating layer, which has a lower flow temperature than the flow temperature of the first layer, is deposited onto the first layer. A photoresist mask is patterned and developed to form a window which exposes an area between the conductive members. The device is preferentially etched such that only the exposed areas of the second insulating layer are removed, leaving the first insulating layer intact. An anisotropic etch is used to remove portions of the first insulating layer, leaving spacers along the edges of the conductive members. The photoresist mask is removed and a heating step is performed which flows the remaining portions of the second insulating layer, but not the first layer. Since the second insulating material remains in only selective areas, the process is termed selective planarization. The method provides the benefit that areas which are to be etched to form contact hole or vias are not planarized, unlike existing blanket planarization methods, and a self-aligned contact is formed between the conductive members to the substrate.

Method for forming a multi-layer semiconductor device using selective

A self-aligned contact is formed in a multi-layer semiconductor device. In one form, conductive members are formed overlying a substrate material and a first insulating layer is deposited overlying the substrate material and the conductive members. A film of material is deposited on the first insulating layer and the film of material is patterned to form a sacrificial plug in an area where a contact is to be made. A second insulating layer is deposited on the device, and the device is made substantially planar. The second insulating layer is etched back to expose the sacrificial plug. The sacrificial plug is removed by selectively etching the device such that the first and second insulating layers are left substantially unaltered. An anisotropic etch of the device is performed to expose an area of the substrate material on which a contact is to be made, and to simultaneously form sidewall spacers along edges of the conductive members. A conductive layer is deposited onto the device and patterned, thereby forming a self-aligned contact.

Process for forming a self-aligned contact structure

A method for differentially etching silicon nitride, preferably formed in a hydrogen free environment, wherein hydrogen is implanted into various regions of the silicon nitride. The silicon nitride may then be etched by a number of different etchants, some of which will etch the implanted regions appreciably faster and others which will etch the non-implanted regions more quickly. This method is especially useful in the fabrication of self-aligned gate devices.

Differential etching of silicon nitride

A method for diffusing a metal dopant into a semiconductor switching device is provided by the use of a rapid thermal heating apparatus. This method provides a procedure for the selectively placing of a metal dopant in a region of the device or circuit. This aids in increasing the manufacturing yields of the switching device, and increases the number of active traps for minority carriers.

Metal redistribution by rapid thermal processing

Improved thin film resistors and electrical devices and circuits with thin film resistors are fabricated utilizing a chromium, silicon, and nitrogen compound formed preferably by rf reactive sputtering of chromium and silicon in a nitrogen bearing atmosphere. An annealing step is used to produce time-stable resistance values and in combination with variations in the partial pressure of nitrogen during sputter deposition to control the temperature coefficient of resistivity to have positive, negative or zero values.

Chromium-silicon-nitrogen thin film resistor and apparatus

Thin film resistor material and method

Chromium-silicon-nitrogen resistor material

Growing community of inventors

Austin, TX, United States of America

Wayne M Paulson