Intel Corporation

Other

Wayne M Needham

Qi-De Qian

Anthony C Miller

Tim Maloney

Aspects of the present disclosure provide for a system. In some examples, the system includes a computing device configured to capture an image depicting dental characteristics of an animal and a server. The server is configured to receive the image from the computing device, determine a plurality of teeth depicted in the image, determine at least one feature associated with at least one of the plurality of teeth, determine an estimate age of the animal based at least partially on the determined plurality of teeth and the at least one feature, and provide the estimated age of the animal.

Machine learning system animal age determination

A method and apparatus for testing integrated circuits is described. The method and apparatus provide a nearly constant power supply current load on the test power supply, and a nearly constant thermal load on the cooling system. This promotes more reliable and repeatable testing of production integrated circuits. A dummy load, in thermal contact with a device under test and the cooling system, consumes a value of current complementary to the current consumed by the device under test, which is under the control of a series of enhanced test vectors.

Method and apparatus for controlling the power and heat output in a device testing system

A self-testing buffer circuit. In one embodiment, the buffer circuit of the present invention provides built in self-testing of input/output circuits on high speed devices without the need for expensive high end testers by switchably coupling the early input stage of a buffer circuit to the late output stage of the buffer circuit to create an oscillating feedback loop during self-test. A counter is used to count the total number of oscillations for a period of time to determine the oscillation rate of the input/output buffer circuit during the self-test. At the end of the count sequence, the count value is scanned out of the counter and it is determined whether the count value is within an expected range. If the count value is not within an expected range, then there is an increased probability of a speed related defect in the buffer circuit.

Method and apparatus for built in self-test of buffer circuits for speed related defects

A method for detecting open circuits in a semiconductor device, more specifically in a static CMOS device. A device to be tested is powered-up and the clock on the device is stopped so that the device enters a quiescent state. Once the device has reached a quiescent state a first current is measured and after a specified period of time a second current is also measured. The first current and the second current are then compared to determine if there is a defect, i.e. an open circuit, in the device. The determination as to whether or not a device is defective is based upon the difference between the first and second current measurements.

Method for detecting opens through time variant current measurement

In one aspect of the present invention, an apparatus is provided for testing a processor running a software program. The apparatus includes a bus having control, data and address lines and a device assigned at least one address. The bus connects the device to the processor. The apparatus includes a multiple input signature register having a plurality of parallel input terminals connected to the data lines. The apparatus includes a control unit having first and second input terminals connected to the address and control lines respectively. The control unit is adapted to enabling the parallel input terminals of the multiple input signature register in response to detecting on the address and control lines at least one preselected triggering event executed by the software program to a preselected address of the device. The apparatus includes a signature comparator adapted to comparing a test signature number from the multiple input signature register to a reference signature number.

Methods and apparatus for system testing of processors and computers

A testing methodology for very large scale integrated circuits, for example, microprocessors having several million transistors. Initially a set of pseudorandom test patterns is selected. During the design of the integrated circuit it is partitioned into functional units and each unit is designed to be verified and tested by the test patterns. During a test mode all of the units of the integrated circuit receives the test patterns in parallel. The output from each unit is coupled to a signature register. The contents of the signature registers are examined following application of the test pattern. This testing methodology lends itself to the simultaneous testing of many integrated circuits.

Apparatus and method for testing integrated circuits

A method and an apparatus for sensing quiescent current in a CMOS integrated circuit. The present invention utilizes circuitry which is not series coupled to the CMOS integrated circuit under test. The quiescent current, commonly referred to as I.sub.DDQ, flows through the supply line during the quiescent state of the CMOS integrated circuit. A magnetic field sensor is located on the substrate near the supply line of the CMOS integrated circuit. The magnetic field sensor detects the magnetic field generated from the supply line by I.sub.DDQ. The magnetic field sensor is coupled to output circuitry located on the substrate which produces a measurement result calibrated to indicate when I.sub.DDQ has a predetermined value.

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Gilbert, AZ, United States of America

Wayne M Needham