Agilent Technologies, Inc.

Hewlett-packard Company

Wayne M Greene

Min Cao

Dietrich Werner Vook

Frederick A Perner

Shawming Ma

Jeremy Alfred Theil

Gary William Ray

Kit M Cham

Francis Joseph

Paul J Vande Voorde

Xin Sun

Charles M C Tan

Malahat Tavassoli

Elizabeth C Carr

Steven A Lupi

Michael B Cox

Frank Perlaki

A semiconductor isolation structure. The semiconductor isolation structure includes a substrate. A first device and a second device are formed within the substrate. An isolation region is formed within the substrate between the first device and the second device. The isolation region includes a deep region which extends into the substrate. The deep region includes a deep region cross-sectional area. A shallow region extends to the surface of the substrate. The shallow region includes a shallow region cross-sectional area. The deep region cross-sectional area is greater than the shallow region cross-sectional area. For an alternate embodiment, the deep region includes an oxide and the shallow region includes a protective wall. The protective wall can be formed from an oxide and a nitride.

Local oxidation of a sidewall sealed shallow trench for providing isolation between devices of a substrate

An imaging device includes a Gray Code generator and an array of pixels. Each pixel includes a complimentary metal oxide semiconductor (&ldquo;CMOS&rdquo;) sensor, a comparator and random access memory (e.g., ferroelectric random access memory). The Gray Code generator is started at the beginning of capture mode and begins providing a sequence of code words. Within each pixel, an output of a CMOS sensor is compared to a threshold, and a code word in the sequence is stored in random access memory when the sensor output crosses the threshold. Thus, the random access memory of each pixel stores a code word that represents the intensity of light detected by its associated CMOS sensor.

Random access memory integrated with CMOS sensors

An array of active pixel sensors. The array of active pixel sensors includes a substrate that includes electronic circuitry. An interconnect structure is formed adjacent to the substrate. The interconnect structure includes a plurality of conductive vias. A plurality of conductive guard rings are formed adjacent to the interconnect structure. Each conductive guard ring is electrically connected to the substrate through at least one of the conductive vias. A plurality of photo diode sensors are formed adjacent to the interconnect structure. Each photo diode sensor is surrounded by at least one of the conductive guard rings. Each photo diode sensor includes a pixel electrode. The pixel electrode is electrically connected to the substrate through a corresponding conductive via. An I-layer is formed adjacent to the pixel electrode. The array of active pixel sensors further includes a transparent conductive layer formed adjacent to the photo diode sensors. An inner surface of the conductive layer is physically connected to the photo diode sensors, and electrically connected to the substrate through a conductive via. The electronic circuitry biases the photo diode sensors and controls a guard voltage potential of the conductive guard rings.

Conductive guard rings for elevated active pixel sensors

An active pixel sensor. The active pixel sensor includes a substrate, an interconnect structure adjacent to the substrate, and at least one photo sensor adjacent to the interconnect structure. At least one photo sensor is formed adjacent to the interconnect structure. Each photo sensor includes a pixel electrode which includes a patterned doped semiconductor layer. An I-layer is formed adjacent to the patterned doped semiconductor layer. A transparent electrode is formed adjacent to the I-layer. A method of forming the active pixel sensor includes forming an interconnect structure over a substrate. Next, a doped semiconductor layer is deposited over the interconnect structure. The doped semiconductor layer is etched forming pixel electrode. An I-layer is deposited over the pixel electrodes. Finally, a transparent conductive layer is deposited over the I-layer.

Elevated pin diode active pixel sensor which includes a patterned doped

A process of growing a dielectric layer includes a step of heating a gas mixture of at least one gas having a first chemical element of oxygen and a second chemical element other than oxygen to a first predetermined temperature to produce reactive precursors of the gas mixture. The reactive precursors are then introduced into a reaction chamber that houses at least one wafer to grow the dielectric layer on the wafer within the reaction chamber at a second predetermined temperature below the first predetermined temperature. A semiconductor manufacturing apparatus of growing the dielectric layer is also described.

Arrangement for growing a thin dielectric layer on a semiconductor wafer

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Los Gatos, CA, United States of America

Wayne M Greene