Digital Equipment Corporation

Compaq Computer Corporation, Inc.

Wayne M Cardoza

Dileep P Bhandarkar

David N Cutler

Richard T Witek

David A Orbits

Michael Seward Harvey

Karen Lee Noel

Richard B Gillett, Jr

Steven D DiPirro

James Alan Woodward

Wendell B Fisher, Jr

Richard Sayde

Anne E McElearney

James R Goddard

Jeffrey E Nelson

Jeffrey M Diewald

William Snaman, Jr

Charles Kaufman

Kathleen D Morse

Dave Cutler

Rich Witek

Dave Orbits

A technique for sharing a resource among a cluster of devices in a computer network. The technique involves generating a vote count that includes votes from voting devices attempting to form a cluster until the vote count reaches a quorum. The technique further involves, when the quorum is reached, selecting a most advanced generation indicator from among the voting devices, advancing the selected generation indicator and storing the advanced selected generation indicator in memory as a cluster generation indicator. Upon the advanced selected generation indicator being stored in memory, the cluster is formed and includes the voting devices. The technique further involves sharing a resource among the voting devices after the cluster is formed.

Computer network cluster generation indicator

Each processor in a multi-processor system includes a process page-table-base register and a system page-table-base register. Each register identifies a different page frame containing a different instance of a top-level subtable in a multi-level page table, and both instances' contents map their respective, different page frames to the same virtual page. A first of the instances, to which the process page-table-base register refers, is used to translate virtual addresses in a process-private range, while the second instance is used for shared-range translation. When a context switch occurs, the content of the process page-table-base register is changed in accordance with the process to whose operation the processor is turning, but that of the system page-table-base register remains unchanged. Parts of the shared space are replicated in different local memory modules, and processors in different locales have different contents in their system page-table-base registers to identify different top-level-subtable instances, which map some shared-space virtual pages to different physical page frames.

Concurrent page tables

An error recovery method and apparatus has specific application in a networking arrangement having a plurality of individual processing nodes which communicate via shared memory space. For error recovery, the system uses a reliable error count, the value of which is maintained by all of the nodes. When an error is detected, the error count is incremented, and all of the active nodes are provided with the new error count. Any of the nodes can run the error recovery method, and may gain exclusive access to the network by acquiring an error recovery spinlock. Once the spinlock is acquired, the node holding the spinlock increments the error count and confirms that all active nodes have received the new error count. The spinlock is thereafter released.

Method for error recovery spinlock in asymmetrically accessed

A virtual memory system is disclosed, providing a virtual address space of virtual addresses simultaneously available to a given process. The virtual address space includes a process private space accessible only to a given process, as well as a shared space of virtual addresses potentially accessible to two or more processes. The process private space includes virtual addresses on one side of a private/shared virtual address boundary, while the virtual addresses within the shared space are on the other side of the private/shared virtual address boundary. The private/shared boundary is ensured to be greater than a predetermined highest process private (or shared) virtual address of a different virtual memory system, and less than or equal to a predetermined lowest shared (or process private) virtual address of that different virtual memory system. Compatibility is ensured for software written for the different virtual memory system, allowing such software to run without modification on the present system. In an example embodiment, the private/shared boundary is set responsive to a user input reflecting a desired ratio between shared and process private space.

Variable split virtual address space allocation with multi-system

A method of remote debugging comprises a first computer system that communicates with a second computer using a network connection. The first computer system controls the remote debugging and comprises a first operating system. The second computer system comprises a second operating system and software being tested. User input, in the form of debug commands, is received using a remote debugger in the first computer system to control the remote debugging session. The remote debugger translates a debug command into messages that are sent from the first computer system to the second computer system. The messages correspond to tasks that the target computer system performs to complete the debug command. During debugging, the target computer system transitions between polling or stopped mode and interrupt-driven mode by transitioning both the target operating system and network hardware in the target computer system that interfaces with the network.

Method and apparatus for testing software on a computer network

A network of processors synchronize modification of a common data structure stored in an asymmetric reflective memory by using a queue. A first processor stores a queue element in a global write-only address space of the reflective memory, the reflective memory to copy the queue element to a local read/write address space of a second processor. The first processor also stores a queue header in the global write-only address space. In response to detecting the queue element, the second processor reads the queue header and then overwrites the queue header with a zero. The reading and writing of the queue header are performed atomically in the local read/write address space of the second processor. The second processor processes the queue element, and marks the queue element as processed in the global address space of the reflective memory.

Method and apparatus for synchronizing data queues in asymmetric

An instruction eases exception handling in a data processing system having one or more parallel pipelined execution units by permitting the central processing unit to complete instructions currently being processed by the execution units, but preventing further instructions from being initiated until all currently executing instructions have been completed and all outstanding exception conditions have been resolved. After all the instructions preceding the DRAIN instruction of the present invention in the program instruction sequence have been executed, the central processing unit can continue to execute the sequential program instructions when no arithmetic exception has been identified, or can invoke an exception handling procedure when an arithmetic exception has been identified. The instruction is typically positioned in an instruction sequence after an instruction that has high degree of probability of resulting in the identification of an arithmetic exception condition. The DRAIN instruction permits the source of the exception to be localized and permits the response to all arithmetic exceptions associated with instructions initiated before the DRAIN instruction, but identified after the execution of the DRAIN instruction, to be handled in the same context environment in which the instruction was initiated.

Method for synchronization of arithmetic exceptions in central

In a data processing system, apparatus and method for controlling the type of processing to which data signal groups can be subjected includes a page table entry format having a multiplicity of field positions for storing signals defining page access rights. In addition to the read/write access control, the signal group access rights can be determined by the current mode of operation of the data processing unit and the intended activity of the addressed instruction or data element (i.e., read, write or execute).

Apparatus and method for main memory unit protection using access and

In a multiprocessor data processing unit, a data element in the main memory unit, that has system wide significance, can have a requirement that this data element be altered in a controlled manner. Because other data processing units can have access to this data element, the alteration of the data element must be synchronized so the other data processing units are not in the process of altering the same data element simultaneously. The present invention includes an instruction that acquires access to an interlock signal in the main memory unit and initiates an interlock in the main memory unit, thereby excluding other data processing units from gaining access to the interlock signal simultaneously. The instruction causes the data element related to the interlock signal to be transferred to the data processing unit where the data element is saved, can be entered in mask apparatus and then have a quantity added thereto. The altered data element is returned to the main memory unit location and the main memory interlock signal is released, thereby completing the instruction.

Apparatus and method for synchronization of access to main memory signal

In a data processing system, an instruction is disclosed that generates a fault when a predetermined register position (e.g., the low or least significant bit position) has a predetermined logic signal (e.g., a logic `0` signal). This instruction provides a mechanism to determine when a Boolean value indicates a presence of a fault condition and provides a mechanism to generate the fault when present. For example, in arrays of memory locations that can be addressed by a program, this instruction can respond to the presence of an array address (or reference) that is outside the prescribed bounds of the array. When an invalid address is identified, a signal is entered in the low (i.e., least significant) bit position of a processor scalar register. The instruction repertoire includes a Fault on Low Bit Clear instruction that tests the contents of the scalar register low bit position, and when a logic `0` signal is found therein, an exception signal is generated and applied to the control program of the data processing system.

Apparatus and method for data induced condition signalling

In a data processing system employing microcode techniques, complex sequences of microinstructions can be initiated by application of a single macroinstruction. These complex sequences of microinstructions are typically noninterruptible and therefore the execution of a macroinstruction is atomic (i.e., executed as a single entity). Data processing systems that do not employ microcode typically have simpler macroinstruction sets that do not provide for a similar atomicity for complex instruction sequences. In order to obtain the same atomicity of instruction execution and to provide a nonmicrocoded data processing system with the capability to execute complex instruction sequences as an atomic operation, the nonmicrocoded data processing system is provided with a third mode, in addition to the (nonprivileged) user mode and the (privileged) kernel mode, of operation that permits the execution of instruction sequences with interrupting events disabled and certain functions and apparatus enabled to facilitate instruction sequence execution.

Providing a data processor with a user-mode accessible mode of

In a data procesing system having a kernel mode (i.e., for executing privileged instructions) and a user mode of operation, apparatus for responding to interrupt conditions includes a first register, subject to the control of the currently executing program for enabling the generation of a mode-related interrupt signal and includes a second register for indicating the presence of a pending mode-related interrupt condition and a third register for requesting a mode-related interrupt be entered in the second register. The mode of operation and the enable and pending interrupt condition registers are monitored and when the signals in the two registers have the appropriate relationship, an interrupt signal is generated to which a control program will respond. The contents of the first register can be controlled by the currently executing program which can control the enabling signal for the currently executing mode. The pending interrupt condition and the request registers may be accessed only from the privileged mode of operation.

Apparatus and method for control of asynchronous program interrupt

In a data processing system employing virtual memory techniques and capable of performing a plurality of overlapping scalar and vector data processing operations, apparatus and method are provided to allow continuation of program execution after one or more vector load/store instructions, which refer to data values that are not currently in memory, receive page faults. At the occurrence of such a page fault, all instructions currently in execution are allowed to be completed, whereupon information summarizing the page fault condition is recorded in memory for use by the operating system software and a vector exception is generated. Operating system software responds to this exception, examines the fault information, causes the missing pages to be read into the main memory unit from the mass storage media, re-executes the exception producing vector instruction(s) and continues with the program execution.

Apparatus and method for recovering from missing page faults in vector

The invention relates to a method and apparatus to minimize the time a data processing system spends on saving and restoring vector processor state data during a context switch. A context switch occurs when execution of an old process is suspended and execution of a current process is begun. The vector state data associated with the old process remains in the vector processor until the current process attempts to execute a vector instruction. When this occurs, the vector state data associated with the old process is saved and vector state data associated with the current process is restored, if the old process is not the same as the current process. If the old process is the same as the current process, there is no need to save and restore any vector state data.

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Amherst, NH, United States of America

Wayne M Cardoza