Hewlett-Packard Development Company, L.p.

Other

Wayne Kever

Samuel D Naffziger

Eric S Fetzer

Eric R DeLano

Kenneth Koch, Ii

A manifold including first and second divider bodies each having a carburetor mounting flange. The first divider body includes a first and a second plenum, and the second divider body includes a third and a fourth plenum. A first pair of runners extends from the first port flange to the first plenum; a second pair of runners extends from the first port flange to the third plenum; a third pair of runners extends from the second port flange to the second plenum; and a fourth pair of runners extends from the second port flange to the fourth plenum. Accordingly, in operation, each plenum will present only one carburetor venturi to the cylinder in a low-RPM, low-throttle opening induction event, thus keeping the peak velocity through the carburetor's venturi high even at low RPM.

Tunnel ram intake manifold for improved low RPM operation

Processes, software and systems asymmetrically shrink a layout for a VLSI circuit design. A first VLSI circuit design layout, defined by a first fabrication process with first design rules, is asymmetrically scaled to a second VLSI circuit design layout defined by a second fabrication process with second design rules. Layouts of one or more leaf cells of the second VLSI circuit design layout are processed to ensure conformity to the second design rules.

Systems and processes for asymmetrically shrinking a VLSI layout

Selective application of solder bumps in an integrated circuit package. Solder bumps are selectively applied in a solder bump integrated circuit packaging process so that portions of a circuit can be effectively disabled. The bumps may be selectively applied either to a die or to the substrate using multiple solder masks, one for each pattern of solder bumps desired or can be otherwise applied in multiple patterns depending upon which portions of the circuitry are to be active and which are to be disabled.

Selective solder bump application

A multiple dispatch processor has several instruction fetch units, each for providing a stream of instructions to an instruction decode and dispatch unit. The processor also has an resource allocation unit, and multiple resources such as combined integer and address execution pipelines and floating point execution pipelines. Each instruction decode and dispatch unit requests resources needed to perform an instruction of the resource allocation unit, which arbitrates among the multiple instruction decode and dispatch units.

Multidispatch CPU integrated circuit having virtualized and modular resources and adjustable dispatch priority

A method for storing lines of data in a data array of a cache memory mapped to a main memory of a processing system. The data array includes data storage lines having equal lengths. The method includes compressing at least one of the lines of data, fitting the compressed line of data within a subsection of one of the data storage lines, and pointing to the subsection using a tag array. When lines of data are stored in compressed form, more lines can fit into the cache, and a probability of a cache hit is increased.

Apparatus and methods for cache line compression

A method of providing critical circuits in a library of circuits, whereby such critical circuits allows designers to apply modifications to them in a controlled manner such that the changes are easy to implement and virtually guaranteed to be correct. The invention comprises a method of performing limited modifications to such critical circuits to alter its characteristics in a controlled manner, and thereafter checking the resulting modified circuit with a circuit simulator for conformance to predetermined specifications that have been assembled for this library critical circuit.

Method for controlling critical circuits in the design of integrated circuits

A compression engine for a cache memory subsystem has a pointer into cache tag memory and cache data memory and an interface coupled to the pointer and capable of being coupled to cache tag memory, and cache data memory. The interface reads tag information and uncompressed data from the cache and writes modified tag information and compressed data to the cache. The compression engine also has compression logic for generating compressed data and generate compression successful information, and tag line update circuitry for generating modified tag information according to the compression successful information and the tag information. Also disclosed is a cache subsystem for a computer system embodying the compression engine, and a method of compressing cache using the compression engine.

Growing community of inventors

Fort Collins, CO, United States of America

Wayne Kever