Intel Corporation

Agere Systems Inc.

Qlogic Corporation

Wayne Genetti

Vladimir K Tamarkin

Brent Ryan Rothermel

Keith Mease

Mark Wessel

Philip Murphy

David Schweitzer

David George Sotak

Some embodiments include apparatus and methods having a circuit board, a device located on the circuit board, a first Peripheral Component Interconnect Express (PCIe) connector located on the circuit board and coupled to the device, and a second PCIe connector located on the circuit board and coupled to the device. The first PCIe connector is arranged to couple to a first connector of an additional circuit board. The second PCIe connector is arranged to couple to a second connector of the additional circuit board.

Peripheral component interconnect express (PCIE) card having multiple PCIE connectors

A cabled midplane interconnect system includes a cabled midplane interconnect having a first connection and a second connection. A first circuit board has a third connection configured to be coupled to the first connection. A second circuit board has a fourth connection configured to be coupled to the second connection. The connection orientations are assigned such that a midplane cable, having a plurality of conductors, couples the first connection to the second connection so that none of the plurality of conductors crosses another of the plurality of conductors.

Midplane interconnect system with conductor twist mitigation

A cabled midplane includes a first support plate along a plane between a first connector set and a second connector set that connect to line cards on either side of the cabled midplane. The first connector set and the second connector set include connector slices. A wiring sub-layer includes cable slices to provide a connection between the first connector slice of a connector of the first connector set to the first connector slice of a connector of the second connector set, such that the first wiring sub-layer connects each connector of the first connector set, through one cable slice, to a connector of the second connector set. Additional wiring sub-layers are added, and a second support plate, parallel to the first support plate, is provided to encase and support the wiring sub-layers between the first support plate and the second support plate. Other apparatuses and methods are described.

High density cabled midplanes and backplanes

Peripheral component interconnect express (PCIe) card having multiple PCIe connectors

Switch systems and method to configure switch systems are disclosed. A switch system includes a first leaf module and a first spine module. The first leaf module includes a plurality of internal ports and external ports. The first spine module includes a plurality of ports. A midplane is configured to couple each of the internal port of first leaf module to a port of a first spine module such that a subset of internal ports of the first leaf module are always coupled to a known subset of first spine module. Other switch systems and methods to configure switch systems are disclosed.

Method and system for multi level switch configuration

System and method to configure switch systems are disclosed. A switch system includes leaf modules with internal ports and spine modules with ports. A midplane includes first layers closer to a first side, second layers closer to a second side and third layers between the first layers and the second layers. The midplane receives the leaf modules and the spine modules about both the first side and the second side. Conductors of the third layers couple internal ports of the leaf modules about one side to a port of spine modules about the other side. Conductors of the first layers couple internal ports of the leaf modules with ports of the spine modules about the first side. Conductors of the second layers couple internal ports of the leaf modules with ports of the spine modules about the second side.

Method and system for multi-level switch configuration

Switch systems and method to configure switch systems are disclosed. A switch system includes a first leaf module and a first spine module. The first leaf module includes a plurality of internal ports and external ports. The first spine module includes a plurality of ports. A midplane is configured couple each of the internal port of first leaf module to a port of a first spine module such that a subset of internal ports of the first leaf module are always coupled to a known subset of first spine module. Other switch systems and methods to configure switch systems are disclosed.

A method of fabricating an IC includes forming a test circuit in/on the wafer to electrically indicate that a correct mask set was used during a revision of the IC design during the manufacturing process. The readout of the circuit enables the manufacturer to immediately identify that an incorrect mask set was used, thereby preventing any improperly fabricated devices from being shipped to the customer. The test circuit may be located either in a primary device area or in the corridors between the devices (ICs). In either case, the test circuit includes a plurality of test devices, each test device corresponding to a version of the mask set in which at least one mast level modification has been made. In one embodiment the test devices are verification arrays, each array including a multiplicity of n electrical paths electrically connected in parallel with one another and extending across n of the N (n&#x2266;N) structural levels of the wafer/IC (e.g., the poly, window and metal levels). Each of the paths includes n actuatable, series-connected elements corresponding to the masks used to form the n structural levels. After the modification of any one of the masks in a particular version of a mask set, selected elements are actuated in the array to indicate a correct mask version. If an incorrect mask set has been used, the test circuit provides one output signal, whereas if the correct mask set was used, the test circuit provides a different output signal. Also disclosed is a semiconductor wafer that includes such a test circuit either within a primary IC area or within a corridor between ICs.

Method of verifying IC mask sets

A method of fabricating an IC includes forming a test circuit in/on the wafer to electrically indicate that a correct mask set was used during a revision of the IC design during the manufacturing process. The readout of the circuit enables the manufacturer to immediately identify that an incorrect mask set was used, thereby preventing any improperly fabricated devices from being shipped to the customer. The test circuit may be located either in a primary device area or in the corridors between the devices (ICs). In either case, the test circuit includes a plurality of test devices, each test device corresponding to a version of the mask set in which at least one mast level modification has been made. In one embodiment the test devices are verification arrays, each array including a multiplicity of n electrical paths electrically connected in parallel with one another and extending across n of the N (n&lE;N) structural levels of the wafer/IC (e.g., the poly, window and metal levels). Each of the paths includes n actuatable, series-connected elements corresponding to the masks used to form the n structural levels. After the modification of any one of the masks in a particular version of a mask set, selected elements are actuated in the array to indicate a correct mask version. If an incorrect mask set has been used, the test circuit provides one output signal, whereas if the correct mask set was used, the test circuit provides a different output signal. Also disclosed is a semiconductor wafer that includes such a test circuit either within a primary IC area or within a corridor between ICs.

Growing community of inventors

Sanatoga, PA, United States of America

Wayne Genetti