International Business Machines Corporation

Rambus Inc.

Hefei Reliance Memory Limited

Micron Technology Incorporated

Qimonda Ag

Qimonda North America Corporation

Infineon Technologies Ag

Wayne Frederick Ellis

Akash Bansal

Frederick Abbott Ware

Kishore Ven Kasamsetty

Lawrence Lai

Wayne S Richardson

William R Tonti

Deepak Chandra Sekar

Thomas Vogelsang

Louis L Hsu

Yohan Usthavia Frans

Oliver Kiehl

Klaus Hummler

Josef Schnell

Lee Ward Collins

Octavian Beldiman

John Atkinson Fifield

Brent Steven Haukness

Jung Pill Kim

Jong Hoon Oh

Claude Louis Bertin

Wayne John Howell

Gary Bela Bronner

Jeffrey H Dreibelbis

Deborah Lindsey Dressler

Julia Kelly Cline

Ely K Tsern

Jack Allan Mandelman

Rajiv V Joshi

Ramachandra Divakaruni

Brian S Leibowitz

Suresh Rajan

Randy William Mann

Howard L Kalter

Mark William Kellogg

Russell J Houghton

Erik L Hedberg

Jerzy Maria Zalesinski

John Welsford Brooks

Robert C Wong

Wagdi William Abadeer

David J Wager

John Ulrich Knickerbocker

Ian P Shaeffer

John Edward Barth, Jr

Mark Vincent Pierson

Steven Cameron Woo

Michael Allen Van Buskirk

Liji Gopalakrishnan

James Marc Leas

Donald Lawrence Wheater

Josef S Watts

Vlad Fruchter

Badih El-Kareh

William T Chen

Pradeep Batra

Mary Elizabeth Weybright

Endre P Thoma

Betina Hold

Duane E Galbi

Joseph Angelo Benenati

John Kim

Thomas E Dinan

David E Douse

John E Barth

Nathan R Hiltebeitel

Theodore M Redman

Brent A Anderson

Carl John Radens

Scott C Best

Subramanian Srikanteswara Iyer

Herbert Lei Ho

William Vincent Huott

Li-Kong Wang

Johnathan E Faltermeier

Paul Christian Parries

Kevin William Gorman

David Meltzer

Brian L Ji

Max Gerald Levy

Thomas M Maffitt

Thomas James Heller, Jr

Jong-Hoon Oh

Erich Klink

Johann Alsmeier

Deok-kee Kim

Shahid Ahmad Butt

Robert E Busch

Hing Wong

Mark David Jacunski

Edward Butler

Scott Josef Bukofsky

Michael Ignatowski

Ronald R Troutman

Patrick R Hansen

Nicholas Martin Van Heel

Knut K Najmann

Oliver Weinfurtner

William R Griffin

Anatol Furman

A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes sideband circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.

Multi-element memory device with power for individual elements

The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.

Timing-drift calibration

In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

Protocol for memory power-mode control

Multi-element memory device with power control for individual elements

Provided are a device comprising a bit cell tile including at least two memory cells, each of the at least two memory cells including a resistive memory element, and methods of operating an array of the memory cells, each memory cell including a resistive memory element electrically coupled in series to a corresponding first transistor and to a corresponding second transistor, the first transistor including a first gate coupled to a corresponding one of a plurality of first word lines and the second transistor including a second gate coupled to a corresponding one of a plurality of second word lines, each memory cell coupled between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of source lines. The methods may include applying voltages to the first word line, second word line, source line, and bit line of a memory cell selected for an operation, and resetting the resistive memory element of the memory cell in response to setting the selected bit line to ground.

2T-1R architecture for resistive ram

2T-1R architecture for resistive RAM

A memory device comprises: an array of memory cells arranged in a plurality of columns in a first direction and a plurality of rows in a second direction, wherein each memory cell in the array comprises: a select transistor, wherein a source terminal of the select transistor is coupled to a source line, and wherein a gate terminal of the select transistor is coupled to a word line, and a memory element coupled in series with the select transistor, wherein a first end of the memory element is coupled to a drain terminal of the select transistor, and wherein a second end of the memory element is coupled to a bit line; and a control circuit configured to provide an unselected source line voltage to source lines of unselected memory cells before providing a selected word line voltage to a word line of a selected memory cell.

1T-1R architecture for resistive random access memory

A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled in series to a first resistive memory element and a second switching element electrically coupled in series to a second resistive memory element. A source of the first switching element and a source of the second switching element receive a common source line signal.

Growing community of inventors

Jericho, VT, United States of America

Wayne Frederick Ellis