Xilinx, Inc.

Rambus Inc.

Wayne Fang

Wayne S Richardson

Parag Upadhyaya

Jafar Savoj

Kun-Yung Chang

Kurt T Knorpp

Andy Chan

Anthony Koon Wong

Kuek-Hock Lee

Jun-Chau Chien

An apparatus relates generally to an injection-controlled-locked phase-locked loop ('ICL-PLL') is disclosed. In this apparatus, a delay-locked loop is coupled to an injection-locked phase-locked loop. An injection-locked oscillator of the injection-locked phase-locked loop is in a feedback loop path of the delay-locked loop.

Injection-controlled-locked phase-locked loop

An apparatus comprises a lock-loop circuit including an oscillator, a frequency detector, a charge pump, and a regulator. The regulator is coupled to provide a regulated signal to the oscillator to control frequency. The oscillator and the frequency detector are coupled to receive a reference clock signal. The reference clock signal is coupled to the oscillator to suppress noise in the oscillator by pulse injection. The frequency detector is coupled to receive an oscillator output from the oscillator.

Phase lock loop with injection pulse control

An edge density detector is disclosed. This edge density detector is to receive a reference frequency signal and a feedback frequency signal. This edge density detector includes a first pulse generator, a second pulse generator, and a charge pump. The first pulse generator is coupled to receive the reference frequency signal and is configured to generate a first pulse signal. The second pulse generator is coupled to receive the feedback frequency signal and is configured to generate a second pulse signal. The charge pump is coupled to receive the first pulse signal and the second pulse signal to provide a control voltage signal. The control voltage signal is a phase independent with respect to the reference frequency signal and the feedback frequency signal.

Edge density detection

A pulse multiplexed output subsystem is disclosed. In one particular exemplary embodiment, the output subsystem may comprise a plurality of pulse generators, a first pair of transistors, and a second pair of transistors, wherein each of the first pair of transistors is coupled to a respective one of a first pair of the plurality of pulse generators, and wherein each of the second pair of transistors is coupled to a respective one of a second pair of the plurality of pulse generators. The output subsystem may also comprise a first pair of resistive loads, wherein each of the first pair of resistive loads is coupled to a respective one of the first pair of transistors and a respective one of the second pair of transistors, and a first current source coupled to the first pair of transistors and the second pair of transistors.

Pulse multiplexed output system

A technique for operating a delay circuit is disclosed. In one particular exemplary embodiment, the technique may be realized by a delay circuit comprising a plurality of data paths. The delay circuit may receive a signal. The delay circuit may also stagger transmissions of the signal through the plurality of data paths. The delay circuit may additionally generate a plurality of signals based on the staggered transmissions. Each of the plurality of data paths in the delay circuit may comprise at least one of an inverter, a logic gate, a flip-flop, a latch, a register, or a resistor-capacitor (RC) delay element.

Technique for operating a delay circuit

An integrated circuit, among other embodiments, includes an output circuit to provide a differential signal on first and second contacts during a first mode of operation, such as in a read or write mode of operation, and a single-ended signal on the first contact during a second mode of operation, such as a test mode of operation. A first variable resistor, responsive to a first control signal, is coupled to a first voltage source and the first contact. A second variable resistor, responsive to a second control signal, is coupled to a second voltage source and the second contact. A first transistor has a first electrode coupled to the first contact, a second electrode coupled to the current source and a gate to receive a first input signal. A second transistor has a first electrode coupled to the second contact, a second electrode coupled to the current source and a gate to receive a second input signal.

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Pleasanton, CA, United States of America

Wayne Fang