Xilinx, Inc.

Wayne Edward Wennekamp

Schuyler E Shimanek

Adam Elkins

Eric E Edwards

Thomas H Strader

Roger D Flateau, Jr

Steven E McNeil

James A Walstrum, Jr

Roy D Darling

Mikhail A Wolf

Steven T Reilly

Joe E Leyba

Brian C Gaide

James M Simkins

Neil G Jacobson

Richard Lewis Walke

Ronald L Cline

Steven K Knapp

John M Thendean

Chidamber Kulkarni

John G O'Dwyer

Richard William Swanson

Chidamber R Kulkarni

James B Anderson

Phillip A Young

Randal M Kuramoto

Joe Eddie Leyba, Ii

Chiao K Hwang

Charles D Laverty

Guoqing Ning

Chin Hua Tan

Shankar Lakka

Sanja Srivastava

Philip A Young

Steven E Mcneil

Adam Elklns

In some examples, a system includes a clock source, a clock distribution network, and a plurality of clock generators. The clock source is configured to generate a global clocking signal. The clock distribution network is configured to fan out the global clocking signal to a plurality of loads. The plurality of clock generators is configured to receive the global clocking signal through the clock distribution network. Each clock generator of the plurality of clock generators is configured to generate a related clocking signal to the global clocking signal from the received global clocking signal. Each clock generator of the plurality of clock generators maybe configured to supply the global clocking signal or the related clocking signal to its respective load of the plurality of loads.

Global clock and a leaf clock divider

An apparatus is disclosed. This apparatus includes a digital signal processing ('DSP') block having a preadder-register block coupled to receive first through fourth input operands. A multiplier is coupled to the preadder-register block to receive a multiplicand operand and a multiplier operand. A first register block is coupled to the multiplier to receive sets of partial products from the multiplier. A second register block coupled to receive the third operand input. An arithmetic logic unit ('ALU') block is coupled to the pre-adder-register block, the first register block and the second register block. The ALU block includes four input multiplexers and an ALU, where the ALU is coupled to receive outputs from each of the four input multiplexers.

Digital signal processing block

A programmable integrated circuit device (IC) can include a configuration controller configured to assert a suspend request signal responsive to an input triggering suspend mode within the programmable IC and a memory controller block coupled to the configuration controller and a memory device. The memory controller block can be configured to place the memory device in self refresh mode in response to the suspend request signal and assert a suspend acknowledgement signal subsequent to placing the memory device in self refresh mode. The configuration controller can continue implementing suspend mode within the programmable IC in response to assertion of the suspend acknowledgement signal.

Memory controller with suspend feature

An embodiment of a technique to capture and locally synchronize data is disclosed. The technique includes receiving first and second signals through a first interface, and receiving a third signal through a second interface where the third signal is unsynchronized with respect to the second signal. The technique further includes detecting a first phase difference between the second and third signals, and generating a fourth signal in a manner so that a second phase difference between the fourth signal and one of the second or third signals is a function of the first phase difference. In addition, the technique includes storing a state of the first signal in response to the fourth signal, and thereafter supplying the stored state of the first signal to the second interface.

Method and apparatus for capturing and synchronizing data

A technique applicable during the transfer of data to and from a memory involves: operating a memory interface using memory access cycles that each transfer a quantity of data D across the memory interface; receiving a request to transfer a quantity of data Q across the memory interface; and calculating a value M as a function of a plurality of parameters, M being a minimum number of the memory access cycles needed to carry out the transfer of the quantity of data Q across the memory interface, wherein the calculating includes determining a logarithm of one of the parameters, and then determining the value M as a function of the logarithm.

Method and apparatus for calculating number of memory access cycles when transferring data to or from a memory

A technique is provided that involves: configuring a clock generation circuit to output a first signal having a first frequency that is one of a plurality of frequencies that are different; generating in a clock section of a further circuit as a function of the first signal a second signal having a second frequency that is one of the plurality of frequencies other than the first frequency; and configuring the clock section to supply to the further circuit a clock signal that is one of the first and second signals.

Method and apparatus for distributing clock signals

An embodiment of a technique to transfer data includes: operating a memory interface using memory access cycles that each include T successive time slots each provided for transfer of B bits of data, where T and B are positive integers; selecting one of first or second predetermined integers as one of T or B; and transferring a quantity of data Q between the memory interface and another interface. The transferring includes: automatically determining a value of M memory access cycles as a function of the one of T or B; causing a data transfer sequence on the memory interface that includes M successive memory access cycles and thus M&#xb7;T time slots; automatically determining a subset of the M&#xb7;T time slots as a function of the one of T or B; and transferring the quantity of data Q through the memory interface during the subset of time slots.

Method and apparatus for transferring data to or from a memory

Some embodiments involve a circuit having first and second interfaces, and configurable structure to identify a selected integer number that is one of a plurality of different integer numbers associated with respective different configurations. In one embodiment, a conversion section organizes lines of the second interface into line groups equal in number to the selected integer number, and carries out a conversion operation in which it supplies to each line group a respective incoming data segment received through the first interface. In another embodiment, a conversion section organizes the lines of the first interface into line groups equal in number to the selected integer number, and carries out a conversion operation in which it supplies to the second interface a respective incoming data segment from each line group.

Method and apparatus for converting data between different word widths using line grouping of data segments

An embodiment of a technique to transfer data between two different interfaces is disclosed. The embodiment of the technique includes: manipulating data arriving at a first data interface with a first word width into data with a second word width; transferring the manipulated data to a second data interface having the second word width; and selecting one of a plurality of different word widths for one of the first or second word widths.

Method and apparatus for transferring data between two different interfaces

A technique is provided for memory control in a device having programmable circuitry, including providing a dedicated memory controller circuit in the device before the programmable circuitry is field programmed. Another technique involves fabricating a device, where the fabricating involves forming programmable circuitry that includes a dedicated memory controller circuit before the circuitry is field programmed.

Method and apparatus for memory control with a programmable device

A device has first circuitry and also second circuitry that includes an interface and command ports that can each receive commands from the first circuitry, each command requesting an information transfer through the interface. A technique relating to the device involves dynamically enabling and disabling at least one of the command ports under control of the first circuitry, and using a priority list specifying an order of priority for a group of the command ports to identify and cause a command to be accepted from the command port of highest priority that contains a command and is currently enabled.

Method and apparatus for arbitration among multiple ports

An apparatus includes a programmable device that has an interface and command ports that can each receive commands, each command requesting an information transfer through the interface. A technique relating to the device involves: selecting during field programming a number of priority definitions; configuring each of the priority definitions during field programming to specify an order of priority for a group of the command ports; and using the priority definitions in succession and, for each of the priority definitions, causing a command to be accepted from the command port of highest priority that contains a command.

Method and apparatus for multi-port arbitration using multiple time slots

Within an integrated circuit comprising a memory controller, a method can include, responsive to determining that the memory controller is performing a refresh operation, calculating a new tap setting according to a new maximum value and an old tap setting of the delay circuit. The new maximum value specifies a number of taps of the delay circuit that approximates a predetermined time span. The method can include dynamically adjusting a delay applied to a signal by a delay circuit according to the new tap setting. The delay circuit generates a delayed signal that is provided to the memory controller.

Dynamic signal calibration for a high speed memory controller

A technique is applicable to a device having programmable circuitry that includes a first interface having a plurality of first address terminals, a second interface having a plurality of second address terminals, and a configurable interconnect structure coupled between the first and second interfaces. The technique includes configuring the interconnect structure during field programming to electrically couple each of the address terminals in a first subset of the first address terminals to respective address terminals in a second subset of the second address terminals according to a selected one of a plurality of different mapping functions.

Method and apparatus for configurable address translation

An integrated circuit, such as a field programmable gate array or other configurable logic device, has an interconnect circuit selectively configurable to operate in a high-speed mode or in a low-power mode. The interconnect circuit is operable from a higher voltage supply or a lower voltage supply to change operating modes without reconfiguring data paths.

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Rio Rancho, NM, United States of America

Wayne Edward Wennekamp