Agere Systems Inc.

Lucent Technologies Inc.

Lsi Corporation

Avago Technologies General IP Pte, Ltd.

Wayne E Werner

Hai Quang Pham

Richard Joseph McPartland

Donald Albert Evans

Ronald James Wozniak

Ross Alan Kohler

Dennis E Dudeck

Makeshwar Kothandaraman

Bijit Thakorbhai Patel

Bernard Lee Morris

Richard Bruce Dell

Thaddeus John Gabara

Douglas D Lopata

Edward Belden Harris

Richard Hogg

Mathew R Henry

Larry Christopher Wall

Richard J Mcpartland

A random number generator circuit includes a first memory having multiple storage elements. Each of the storage elements has an initial state corresponding thereto when powered up by a voltage supply source applied to the first memory. The first memory is operative to generate a first signal including multiple bits indicative of the respective initial states of the storage elements. The random number generator circuit further includes an error correction circuit coupled to the first memory. The error correction circuit is operative to receive the first signal and to correct at least one bit in the first signal that is not repeatable upon successive applications of power to the first memory to thereby generate a second signal. The second signal is a random number that is repeatable upon successive applications of power to the first memory.

Secure random number generator

Techniques for forming a first electronic circuit including a plurality of instances of a repeatable circuit element include the steps of: obtaining a total number of instances of the repeatable circuit element in a design of an IC including the first electronic circuit and at least a second electronic circuit; and configuring at least one functional parameter of the first electronic circuit as a function of the total number of instances of the repeatable circuit element in the IC to thereby satisfy a prescribed minimum composite manufacturing yield of the IC and/or at least one specification of the IC under prescribed operating conditions.

Optimization of circuits having repeatable circuit instances

A memory circuit includes a memory including a plurality of primary memory elements, and an error correction circuit coupled to the memory and operative to detect an error in at least one of the primary memory elements and to provide corrected data corresponding to the primary memory element. The memory circuit further includes at least one spare memory element and a control circuit operative to replace at least one of the primary memory elements with the spare memory element as a function of results generated by the error correction circuit.

High-reliability memory

An IC adapted for self-monitored burn-in includes a first memory and at least one BIST circuit coupled to the memory and operative to test the IC by executing a burn-in test and to generate test results indicative of at least one parameter of the burn-in test. The test results are at least temporarily stored in the first memory as a function of a first control signal.

Integrated circuit self-monitored burn-in

A memory device comprises a memory array and error correction circuitry coupled to the memory array. The error correction circuitry is configured to identify, in a data word retrieved from the memory array, at least one bit position corresponding to a predetermined defect location in the memory array, and to generate a corrected data word by automatically inverting a logic value at the identified bit position. This automatic logic inversion approach is particularly well suited for use in correcting output data errors associated with via defects and weak bit defects in high-density ROM devices.

Memory device with error correction based on automatic logic inversion

A memory device comprises a memory array and a phase distribution circuit coupled to the memory array. In one aspect, the phase distribution circuit is operative to control respective durations of a precharge phase and an active phase of a memory cycle of the memory array based on relative transistor characteristics of a tracked precharge transistor of a first conductivity type and a tracked memory cell transistor of a second conductivity type different than the first conductivity type. For example, the phase distribution circuit may comprise a first tracking transistor of the first conductivity type for tracking the precharge transistor of the first conductivity type and a second tracking transistor of the second conductivity type for tracking the memory cell transistor of the second conductivity type. The relative transistor characteristics may comprise relative strengths of the tracked precharge and memory cell transistors.

Memory device with phase distribution circuit for controlling relative durations of precharge and active phases

A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform at least a partial word write operation and a read operation, with the partial word write operation comprising a read phase and a write phase. The write phase of the partial word write operation occurs in the same clock cycle of the memory device as the read operation by, for example, time multiplexing bitlines of the memory array within the clock cycle between the write phase of the partial word write operation and the read operation. Thus, the partial word write operation appears to a higher-level system incorporating or otherwise utilizing the memory device as if that operation requires only a single clock cycle of the memory device.

Memory device with error correction capability and efficient partial word write operation

In accordance with exemplary embodiments, a multi-level flash memory employs error correction of systematic errors when reading multi-level flash memory. Error correction includes i) detection of each systematic error, ii) feedback of the systematic error to circuitry within the memory, and iii) subsequent adjustment within that circuitry to cause a correction of systematic error in the output signal of the multi-level flash memory.

Systematic error correction for multi-level flash memory

A memory circuit includes a plurality of memory cells and a plurality of bit lines and row lines connected to the memory cells for accessing selected memory cells. The memory circuit includes a programmable voltage source adapted for connection to at least one bit line and operative to precharge the bit line to a prescribed voltage level prior to accessing a selected one of the memory cells coupled to the bit line. A control circuit coupled to the bit line is operative to oppose discharge of the bit line during at least a portion of a given memory read cycle. A tracking circuit connected to the control circuit is operative to control a delay in activation of the control circuit and/or a duration of time the control circuit is active as a function of a parameter affecting signal development time of a data signal on the bit line.

Tracking circuit for reducing faults in a memory

A nonvolatile memory comprising an array of memory cells and sense amplifiers, each sense amplifier using a keeper circuit to provide an amount of current to compensate for bit line leakage current in the memory array. The amount of current from the keeper depends on the temperature of the memory and the speed of the process used to make the memory.

Process and temperature tolerant non-volatile memory

Techniques for testing a semiconductor memory device are provided. The memory device includes a plurality of memory cells and a plurality of row lines and column lines connected to the memory cells for selectively accessing one or more of the memory cells. The method includes the steps of: applying a first voltage to at least a given one of the row lines corresponding to at least a given one of the memory cells to be tested, the first voltage being selected to stress at least one performance characteristic of the memory device, the first voltage being different than a second voltage applied to the given one of the row lines for accessing at least one of the memory cells during normal operation of the memory device; exercising the memory device in accordance with prescribed testing parameters; and identifying whether the memory device is operable within prescribed margins of the testing parameters.

Method and apparatus for testing a memory device

Certain embodiments of the inventions provide an integrated circuit (IC) having a processor operatively coupled to a PVT (process-voltage-temperature) source and an adjustable memory. The processor receives from the source an input characterizing the present PVT condition and generates a command for the memory based on that input. In response to the command, the memory adjusts its internal circuit structure, clock speed, and/or operating voltage(s) to optimize its performance for the present PVT condition. Advantageously, the ability to adjust the memory so that it can maintain its functionality and deliver an acceptable level of performance under unfavorable PVT conditions provides additional flexibility in choosing circuit design options, which can produce area savings and/or increase the yield of acceptable ICs during manufacture.

Integrated circuit having a memory with process-voltage-temperature control

An electronic circuit includes multiple circuit elements arranged into multiple distinct subdivisions, each subdivision having a separate voltage supply connection for conveying power to the subdivision. The electronic circuit further includes a controller including multiple outputs, each of the outputs being connected to a corresponding one of the voltage supply connections. When a given one of the subdivisions does not include a weak circuit element, the controller supplies a first voltage level to the given subdivision via the corresponding voltage supply connection. When the given subdivision includes at least one weak circuit element, the controller is operative to supply at least a second voltage level to the given subdivision via the corresponding voltage supply connection, the second voltage level being greater than the first voltage level.

Method and apparatus for increasing yield in a memory device

A memory device comprises a memory array, at least one buffer coupled to the memory array, and test circuitry coupled to the buffer. The buffer comprises switching circuitry configured to multiplex first and second inputs of the buffer to a given output of the buffer based at least in part on a control signal generated by the test circuitry. The control signal is generated as a function of both a test signal indicative of a test mode of operation of the memory device and a power-down signal indicative of a power-down mode of operation of the memory device. The buffer further comprises current reduction circuitry responsive to the control signal for reducing an amount of current consumed by the buffer in the power-down mode of operation. The buffer may comprise an input data buffer or an address buffer of the memory device.

Memory device with reduced buffer current during power-down mode

A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform a partial word write operation in which an error correction code encode process for the given retrieved word is initiated prior to completion of an error correction code decode process for the given retrieved word based on an assumption that the error correction code decode process will not indicate an error in the given retrieved word. If the error correction code decode process when completed indicates an error in the given retrieved word, the error in the given retrieved word is corrected in the error correction circuitry, and the error correction code encode process is restarted using the corrected word. The error correction code decode process and an associated correct process are thereby removed from a critical timing path of the partial word write operation.

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Coopersburg, PA, United States of America

Wayne E Werner