Hewlett-packard Development Company, L.P.

Hewlett-packard Company

Wayne E Bradburn

Eugene A Roylance

James G Bearss

Arlin R Jones

Lower resolution source data is synthesized to a higher resolution format for subsequent rendering on a lower resolution output device. Synthesis occurs by selecting or generating and using a synthesis template that represents a configuration of a plurality of pixel data in the higher resolution format into which the lower resolution source data is to be synthesized. A working or active pixel is identified from the lower resolution source data, a synthesis template is selected, and then the synthesis template pixel data is substituted for the working pixel for rendering on the output device. The synthesized higher resolution data is rendered in a manner such that dots represented by the synthesized data are formed interstitially relative to scan lines of the given lower raster/resolution capability of the output device. The working pixel is identified in the lower resolution data by recognizing a configuration of a plurality of pixel data adjacent the working pixel. The synthesis template comprises at least a two by two cell matrix for pixel placement in the higher resolution format. The synthesis template pixel placement is formed to provide an apparent merge of the pixel data in the higher resolution format with the adjacent pixel data of the lower resolution format data.

Programmable mapping of lower resolution digital data to a higher resolution for output on a lower resolution device

A pulse width modulator includes a clock operative to count successive discrete time intervals having a period equal to a desired full pulse width, and configured to generate a clock signal. The pulse width modulator also includes an adjustable delay line comprising a plurality of delay line elements, each delay line element operative to generate a clock signal at a specific location, which when combined with a transitional instruction, will produce a modulated output that has a plurality of transitions within the clock period. The pulse width modulator further includes processing circuitry configured to receive the clock signal and a pulse code input and operative to select one of the delay line elements to generate a clock signal at a specific location to produce a single modulated output that transitions at a desired modulated frequency. A method is also provided.

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Eagle, ID, United States of America

Wayne E Bradburn