Nvidia Corporation

Nvidia U.S. Investment Company

Wayne Douglas Young

Franck Diard

Philip Browning Johnson

Brijesh Tripathi

Michael A Ogrinc

Adam E Levinthal

Herbert O Ledebohm

Stephen M Ryan

Matthew Nicholas Papakipos

Duncan Andrew Riach

Leslie E Neft

Paul MacDougal

Johnson Philip Browning

Method, apparatuses, and systems are presented for processing a sequence of images for display using a display device involving operating a plurality of graphics devices, including at least one first graphics device that processes certain ones of the sequence of images, including a first image, and at least one second graphics device that processes certain other ones of the sequence of images, including a second image, delaying processing of the second image by the at least one second graphics device, by a specified duration, relative to processing of the first image by the at least one first graphics device, to stagger pixel data output for the first image and pixel data output for the second image, and selectively providing output from the at least one first graphics device and the at least one second graphics device to the display device.

Display balance / metering

Error accumulation dithering is used to generate images of lower color resolution from input data of higher color resolution. A target color is received at high resolution for a current pixel of the image. The target color is intermediate between a first color and a second color at a low color resolution. One of the first color and the second color is selected as a final pixel color, based on whether an accumulated error determined from previous pixels is above or below a threshold amount. After selecting the final pixel color, an updated accumulated error is provided to the next pixel.

Error accumulation dithering of image data

An isochronous processor includes a state register, a functional unit, a control module, and an activation unit. The state register includes an arm buffer and an active buffer. The functional unit performs a transformation operation on the data stream in response to an active value of the control parameter obtained from the active buffer. The control module updates the arm value of the control parameter in the arm buffer in response to control instructions. The activation unit detects a load event propagating with the data stream and transfers the parameter value from the arm buffer to the active buffer in response to the load event. During this transfer, the control module is inhibited from updating the arm buffer.

Isochronous pipelined processor with deterministic control

Coherence of displayed images is provided for a graphics processing systems having multiple processors operating to render different portions of a current image in parallel. As each processor completes rendering of its portion of the current image, it generates a local ready event, then pauses its rendering operations. A synchronizing agent detects the local ready event and generates a global ready event after all of the graphics processors have generated local ready events. The global ready signal is transmitted to each graphics processor, which responds by resuming its rendering activity.

Coherence of displayed images for split-frame rendering in multi-processor graphics system

Method, apparatuses, and systems are presented for processing an ordered sequence of images for display using a display device, involving operating a plurality of graphics devices, including at least one first graphics device that processes certain ones of the ordered sequence of images, including a first image, and at least one second graphics device that processes certain other ones of the ordered sequence of images, including a second image, the first image preceding the second image in the ordered sequence, delaying at least one operation of the at least one second graphics device to allow processing by the at least one first graphics device to advance relative to processing by the at least one second graphics device, in order to maintain sequentially correct output of the ordered sequence of images, and selectively providing output from the graphics devices to the display device.

Sequencing of displayed images for alternate frame rendering in a multi-processor graphics system

Display balance/metering

Apparatus, system, and method for detecting AC-coupled electrical loads of a set of digital-to-analog converters are described. In one embodiment, a processing apparatus includes a digital-to-analog converter. The processing apparatus also includes a pulse generation module connected to the digital-to-analog converter, and the pulse generation module is configured to direct the digital-to-analog converter to transmit a pulse of electrical energy. The processing apparatus further includes a load detection module connected to the digital-to-analog converter, and the load detection module is configured to determine a connection status of the digital-to-analog converter based on a degree to which the pulse of electrical energy is reflected during a transient response time period.

Apparatus, system, and method for detecting AC-coupled electrical loads

An output pipeline for a video processing device provides supersampling of the output data the digital domain to eliminate or reduce unwanted frequency components in an analog output signal. An encoder converts a pixel stream to digital sample values for a target analog signal at a base sampling rate. The base data stream is supersampled, and the supersampled data is provided to a digital to analog converter The supersampling rate can be selected so as to provide substantial attenuation of a higher frequency echo in the analog output signal.

Supersampling of digital video output for multiple analog display formats

A graphics processing apparatus includes an output pipeline including a set of memory clients. The graphics processing apparatus also includes a memory controller connected to the output pipeline. The memory controller is configured to retrieve data requested by respective ones of the memory clients from a memory. The graphics processing apparatus further includes a buffering module connected between the memory controller and the output pipeline. The buffering module includes a buffer including a buffering space shared by the memory clients. The buffering module also includes a buffer controller connected to the buffer. The buffer controller is configured to: (1) dynamically assign portions of the buffering space to respective ones of the memory clients; (2) coordinate storage of the data in the assigned portions; and (3) coordinate delivery of the data from the assigned portions to respective ones of the memory clients.

Apparatus, system, and method for delivering data to multiple memory clients via a unitary buffer

Apparatus, system, and method for delivering data to multiple memory clients are described. In one embodiment, a graphics processing apparatus includes an output pipeline including a set of memory clients. The graphics processing apparatus also includes a memory controller connected to the output pipeline. The memory controller is configured to retrieve data requested by respective ones of the set of memory clients from a memory. The graphics processing apparatus further includes a buffering module connected between the memory controller and the output pipeline. The buffering module includes a unitary buffer and a buffer controller connected to the unitary buffer. The buffer controller is configured to coordinate storage of the data in the unitary buffer, and the buffer controller is configured to coordinate delivery of the data from the unitary buffer to respective ones of the set of memory clients.

A system adjusts floating-point-valued images prior to conversion to a display signal so that the dynamic range of the display device is effectively used. Images are adjusted using transfer functions to create an adjusted image within the dynamic range of the display device. The adjusted image also has a frequency distribution of pixel values to maximize the perception of visual detail. The system generates transfer functions from statistical attributes of one or more images. The transfer functions are applied to images on the fly as they are converted into a display signal. The statistical attributes of the image are computed on the fly as it is converted into a display signal. A first transfer function is applied to an image to produce an adjusted image in parallel with the generation of a second transfer function to be applied to a future image.

Automatic adjustment of floating point output images

An apparatus for graphics processing unit, which includes a memory for storing pixel data in a red, green and blue (RGB) color space and a display pipeline. The display pipeline includes an RGB color space to a luminance color, blue color difference and red color difference (YCbCr) color space converter module configured to convert the pixel data from the RGB color space to the YCbCr color space. The RGB to YCbCr color space converter module generates a luminance color component (Y) of the pixel data by adding &#xbc; of a red color (R) component of the pixel data to &#xbd; of a green color (G) component of the pixel data and &#xbc; of a blue color (B) component of the pixel data. The luminance color component (Y) of the pixel data may be determined by left shifting the green color (G) component of the pixel data by one bit, adding the result to the red color (R) component of the pixel data and the blue color (B) component of the pixel data, and right shifting the sum by two bits.

Minimalist color space converters for optimizing image processing operations

A method and system are provided for efficiently implementing a dual finite impulse response (FIR) filter to vertically filter video data. A unique feedback mechanism enables multi-filter performance while implementing fewer actual filters and accompanying line delays than required in the available art. Advantageous placement of arithmetic elements is used to compensate for approximation error introduced by the feedback mechanism, resulting in substantially undiminished circuit performance in a more efficient circuit than currently available.

Growing community of inventors

Milpitas, CA, United States of America

Wayne Douglas Young