Nvidia Corporation

Wayne D Young

Michael A Ogrinc

Duncan Andrew Riach

Brijesh Tripathi

One embodiment of the present invention sets forth a system for generating multiple video output signals from a single video pipeline within a graphics processing unit. Pixel data from more than one display surface is retrieved and multiplexed before being transmitted to a video pipeline for processing. The resulting video pixel data is routed to video output encoders, which selectively accept the video pixel data for transmission to attached display devices.

Multiple simultaneous unique outputs from a single display pipeline

One embodiment of a configurable multi-tap filter includes a parallel-to-serial formatter configured to transform a pixel stream into a first component pixel stream and a second component pixel stream, a configurable memory that includes a first channel and a second channel, wherein pixels from the first component pixel stream are stored in the first channel and pixels from the second component pixel stream are stored in the second channel, and a multi-tap filter configured to process a component of a pixel from the first channel and a like component of a pixel from the second channel. In various embodiments, the configurable multi-tap filter may be implemented as a two-tap, three-tap or five-tap filter and may be used to process either RGB or YUV pixels streams. One advantage of the disclosed configurable multi-tap filter is that it uses memory more efficiently than prior art filters.

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Thatcham, United Kingdom

Wayne D Young