Unisys Corporation

Wayne D Ward

David R Johnson

Charles R Caldarale

David C Johnson

Merwin H Alferness

Ralph E Sipple

James R McBreen

Hans Christian Mikkelsen

Kelvin S Vartti

John Steven Kuslak

Joseph P Kerzman

Peter B Criswell

Kenneth L Engelbrecht

Mark D Aubel

Thomas D Hartnett

Richard M Shelton

Donna J Plunkett

Francis A Stephens

James W Douglas

Multi-processor computer systems with multiple levels of cache memories are slowed down in trying to process software locks for common functions. This invention obviates the problem for the vast majority of transactions by providing an alternate procedure for handling so-called communal locks differently from ordinary software locks. The alternative procedure is not used for ordinary (non communal software lock) data and instruction transfers. The function of the CSWL (Communal SoftWare Lock) is actually accomplished at a specific cache to which an individual CSWL is mapped to, rather than sending the lock to the requesting process, which also enhances efficiency.

Method for processing communal locks

In a computer system a system of exchanging tokens for queue banks is created that permits a requester to directly specify which queue bank is wanted. Only the desired queue bank is withdrawn from a queue bank repository to accomplish this and no sorting or FIFO handling of queue banks is needed. The system uses a schema similar to a coat check room, where the requester is given a token when the requestor wants to deposit a queue bank into the queue bank repository. The queue bank repository returns the queue bank when the token is returned by the requester. In its most efficient form, two machine-level instructions handle the entire operation, a withdraw instruction and a deposit instruction.

Queue bank repository and method for sharing limited queue banks in memory

In order to implement alternative pathways and procedures for handling a separate set of software locks, an arrangement of circuits is described. These circuits allow for generating and handling specific requests for communal software locks without additional software development through pathways and procedures separate from ordinary lock handling operations. A side door communications pathway is set up to handle the communal locks separately from the ordinary data transfer pathways through which ordinary software locks get handled. Supporting and controller circuits handle the locking and unlocking process as well as communicating results of lock requests back to requesters.

Communal lock processing system for multiprocessor computer system

The current invention provides an improved system and method for locking shared resources. The invention may operate in a data processing environment including a main memory system coupled to multiple instruction processors (IPs). Lock-type instructions are included within the hardware instruction set of ones of the IPs. These lock-type instructions are executed to gain access to a software-lock stored at a predetermined location within the main memory. After activating the software-lock, further, indivisible execution of the lock-type instruction causes one or more addresses associated with the software-lock to be retrieved. These addresses are used as pointers to, in turn, retrieve the data signals protected by the software-lock. Requests for the protected data signals are issued automatically by the hardware on behalf of the requesting IP, and the IP is allowed to continue instruction execution.

Lock management system and method for use in a data processing system

Multi-processor computer systems with multiple levels of cache memories are given an alternate pathway for handling highly contended-for locks. These are called communal locks. The alternate pathway allows for alternate processing schemas that do not impede the performance of the overall system as is otherwise the case in such computer systems where contended-for locks bounce back and forth between contending caches, crimping storage bus bandwidth and system performance. The alternative pathway is not used for ordinary (non communal software lock) data and instruction transfers.

Multiprocessor computer system for processing communal locks employing mid-level caches

Instruction processor and method supporting dual-mode execution of computer instructions. In various embodiments, certain instructions are executable in one of two modes. The first mode is compatible with the native instruction set and data words, and the second mode is an adaptation suitable for platform independent instructions. A control word RAM is addressed by the operation code of an instruction, and each word in the control word RAM includes an address into a microcode RAM. The address into the microcode RAM is manipulated in accordance with the various embodiments to reference either a first set of microcode for native instructions and data words, or a second set of microcode for execution in a platform-independent mode.

Dual microcode RAM address mode instruction execution using operation code RAM storing control words with alternate address indicator

A system and method for increasing processing performance in a computer system by asynchronously performing system activities that do not conflict with normal instruction processing, during inactive memory access periods. The computer system includes at least one instruction processor to process instructions of an instruction stream, and a memory to store data. One or more inactive data blocks in the memory are identified, and a list of addresses corresponding to the identified inactive data blocks is generated. Available computing cycles occurring during processing in the computer system are identified, such as processing stalls and idle memory write periods. The inactive data blocks associated with the list of addresses are initialized to a predetermined state, during the available computing cycles. Addresses corresponding to those initialized data blocks are then made available to the computing system to facilitate use of the data blocks.

Method and apparatus for increasing computer performance through asynchronous memory block initialization

A system and method for adding a queue entry containing message data to a queue shared by communicating, sequential processes includes an enqueue instruction. The enqueue instruction attaches a queue entry to either the tail or the head of the shared queue, as specified by an application programmer. Execution of the enqueue instruction includes blocking access to the queue by other processes, updating queue linkages, activating processes waiting on entries being made to the queue, monitoring interrupts, and validating the appropriate queue data structures. If desired, in lieu of adding a queue entry containing message data to the queue, the enqueue instruction inserts an event indicator into the shared queue structure, thereby providing synchronization capabilities between communicating processes.

Enqueue instruction in a system architecture for improved message passing and process synchronization

A system and method for interprocess communication between concurrently executing, cooperating sequential processes in a digital computer system uses a shared memory queue as a mechanism for message passing and process synchronization. Data to be transferred from a sending process to a receiving process is stored in a queue entry which is visible in the virtual address space of the first process. The queue entry is added to a queue by the sending process directing the processor to execute an enqueue instruction. The receiving process removes the queue entry from the queue by directing the processor to execute a dequeue instruction. The receiving process then has direct access and visibility to the contents of the queue entry without having to copy the data into its virtual address space. Instead of sending data in a queue entry, a sending process may send an event indicator and no data. The receiving process may then wait on an empty queue until an event notification is received in a queue entry enqueued to the queue. Protection is provided by the system to prevent unauthorized access to the queue by other processes active in the system.

System architecture for improved message passing and process

A system and method for providing high speed emulation of a computer system by transforming selected target instructions and bypassing target instruction decoding for those target instructions which have been transformed. A target computer system, controlled by a plurality of target instructions, is emulated on an emulation host computing system. Target instructions are successively loaded into the emulation host computing system in the order that the target instructions would be executed. The target instructions are decoded to identify the functions designated by the target instructions, and these functions are executed by the emulation host computing system. Emulation information is assigned to selected target instructions, where the emulation information controls execution of these selected target instructions, referred to as transformed instructions. Software routines identified by the emulation information are initiated for these transformed instructions, where the software routines execute the functions of the target instruction in the machine language of the emulation host computing system.

Selective emulation interpretation using transformed instructions

A multiple-word virtual address flexibly expands the virtual address space of a computer system without requiring the modification of the word size of the computer system. In a memory system having a virtual memory mapped to an absolute memory, the virtual memory is divided up into multiple levels each having a plurality of memory banks. Each memory bank has a plurality of words. The multiple-word virtual address provides a plurality of words for specifying the virtual memory level, memory bank, and offset word within the memory bank, to describe a selected memory location. Special instructions are added to the instruction set architecture to set up a window of program visibility, called a peephole, into a selected area of the expanded virtual memory. Existing programs are compatible with the multiple-word addressing scheme, and can also reference virtual memory through a defined peephole. New programs using multiple-word virtual addresses can still call procedures requiring single word virtual addresses.

Flexible expansion of virtual memory addressing

A system and method for removing a queue entry containing message data from a queue shared by communicating, sequential processes includes dequeue (DEQ) and dequeue or wait (DEQW) instructions. The dequeue instruction removes a queue entry from the head of the shared queue, thereby providing access to the message data contained in the queue entry to the dequeuing process. The dequeue or wait instruction removes a queue entry from the shared queue if there is one, otherwise it suspends the execution of the dequeuing process until an entry is enqueued to the queue. If an event is selected by the dequeuing process, the dequeuing process is suspended until notification of the event is detected in the shared queue. Execution of the dequeue and dequeue or wait instructions include blocking access to the queue by other processes, updating queue linkages, deactivating processes waiting on entries or events being made to the queue, monitoring interrupts, and validating the appropriate queue data structures.

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New Brighton, MN, United States of America

Wayne D Ward