Rambus Inc.

Dbtag, Inc.

The University of North Carolina at Chapel Hill

Wayne D Dettloff

John M Wilson

Lei Luo

Jared L Zerbe

Brian S Leibowitz

John Cronan Eble, Iii

Barry William Daly

Jihong Ren

Teva J Stone

Hsuan-Jung Su

Pravin Kumar Venkatesan

Kashinath Ullhas Prabhu

Makarand Ajit Shirasgaonkar

John Wood Poulton

Amir Amirkhany

Carl William Werner

Jade M Kizer

Kun-Yung Chang

Aliazam Abbasfar

Kambiz Kaviani

Chaofeng Huang

Leandra Vicci

William E Batchelor

Michael Steer

Robert A Heaton

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented 'fast turn-on' bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Method and apparatus for source-synchronous signaling

A single-ended receiver includes an internal voltage generation circuit to set a first internal reference voltage (Vref). A model voltage generation circuit is configurable to receive an external reference voltage to be calibrated during an initial calibration. The model voltage generation circuit is configurable to track an offset value for voltage-temperature (VT) drift and the offset value is applied to the internal voltage generation circuit to calibrate the internal Vref during a periodic calibration of the single-ended receiver.

Data independent periodic calibration using per-pin VREF correction technique for single-ended signaling

AC-coupled termination and equalization, including transmit equalization and/or receive equalization, are combined to create a high bandwidth channel that requires no special coding and consumes no or negligible DC current.

Equalizer-compensated AC-coupled termination

A receiver circuit to receive signals from first and second pairs of transmission lines includes first and second interfaces, each with first and second input nodes to receive respective signals. The receiver circuit also includes a resistor network with first, second, third, and fourth resistive elements. The first and second resistive elements are each connected between the input nodes of a respective interface. The third and fourth resistive elements each include a pair of resistors connected in series between the input nodes of a respective interface, and an intermediate node between the resistors. The intermediate nodes are connected to an AC ground. The receiver circuit further includes a differential amplifier with first and second inputs coupled respectively to the first and second interfaces and an output to provide a signal derived from common mode components of the signals received at the input nodes.

Receiver resistor network for common-mode signaling

A voltage mode transmitter equalizer has high efficiencies, yet consumes substantially constant supply current from the power supply and provides constant back-match impedance. The voltage mode transmitter equalizer is configured such that the output voltage of the signal to be output on a pair of transmission lines can be controlled according to the input data, but its return impedance is substantially matched to the differential impedance of the transmission lines and it draws substantially constant supply current from the power supply regardless of the output voltage of the signal. Further, an equalizer for a voltage-mode transmitter provides fine-granularity equalization settings by employing a variable pull-up conductance and a variable pull-down conductance. Conductance is varied by selectively enabling a plurality of conductance channels, at least some of which have resistance values that are distinct from one another.

Voltage mode transmitter equalizer

Conventional bias circuits exhibit a number of limitations, including the time required to power-up a bias circuit following a low-power state. Large current surges in the supply network induce ringing, further complicating a power-up process. Example embodiments reduce power-up time and minimize current surges in the supply by selectively charging and discharging capacitance to the circuit during power-up and power-down of the bias circuit.

Fast power-on bias circuit

High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such 'differential' or 'non-uniform' sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested &#x201c;DAC within a DAC&#x201d; arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.

High resolution output driver

A data systempermits bus encoding based on frequency of the bus; an encoding scheme may be implemented to avoid undesirable frequency conditions such as a resonant condition that may lead to degradation in system performance. The device or integrated circuit will typically include an encoder; in one embodiment, the encoder is a data bus inversion (DBI) circuit that selectively inverts all lines of a data bus. A detector that may include a band-pass or stop-band filter that, for example, evaluates data for transmission on the bus to detect frequency, for example, a predetermined frequency or a frequency range. The detector provides a control signal for the encoder to selectively apply an encoding scheme as a function of frequency.

Frequency responsive bus coding

Methods and systems for compensating magnetic current loops provide current magnitude and phase uniformity within the magnetic current loops. A magnetic current loop is divided into k sections. Each of the k sections has a series reactance. Series reactive compensation is added to each of the k sections such that the reactive compensation substantially cancels the series reactance of each section. Adding reactive compensation to the loop that cancels the series reactance of each section of the loop provides current magnitude and phase uniformity along the loop at any given instant in time. As a result, the magnitude and phase of the magnetic field at a point in space can be controlled with precision to achieve a desired result, such as precise field cancellation or precise field generation.

Methods and systems for reactively compensating magnetic current loops

First and second spaced apart in-phase current loops at least partially overlap in the axial direction. The first and second current loops may be first and second arrays of in-phase current loops that are spaced apart and at least partially overlap in the axial direction. First and second arrays of arrays also may be provided that are spaced apart from one another and that at least partially overlap in the axial direction. Desirably high mid-field strength may be provided without violating guidelines for far field radiation in the axial direction or in the plane of the loops. A third array of in-phase current loops, an array of third in-phase current loops and/or an array of arrays of third in-phase current loops also may be provided that spaced apart from and at least partially overlapping the second loops in the axial direction, opposite the first loops. Third and fourth arrays of in-phase current loops also may be provided that are spaced apart from one another, at least partially overlap one another in the axial direction, and have different orientation than the first and second current loops, to reduce and preferably minimize nulls in the near field and mid field. A receive antenna also may be provided between the overlapping portions of the first and second current loops. By providing a receive antenna at this position, the effects of the fields that are produced by the current loops on the receive antenna may be reduced and preferably minimized.

Growing community of inventors

Cary, NC, United States of America

Wayne D Dettloff