Unisys Corporation

Wayne C Datwyler

Paul B Ricci

Dan T Tran

Long V Ha

The logic circuitry of an IC chip is connected to JTAG register chains which hold state information on each portion of the logic circuitry therein. A JTAG Tracker Module is connected to the controls of each of the JTAG register chains enabling a programmer-operator to read the present state of each JTAG register chain and enabling a readout of the logic circuits condition in a single clock period.

Method and system for tracking the state of each one of multiple JTAG

A single chip data path gate array interface links a central processing unit, operating at a first clock rate and single word protocol, to dual system busses operating at a second clock rate and multiple-word protocol. The data path interface holds command, data and message registers, controlled by external logic, in an input channel pathway and an output channel pathway. The interface chip is basically limited to registers and multiplexers making it flexible for use in different architectures such as both Store-Through and Non-Store-Through cache protocols. In addition, such a simplified chip is simple to fabricate and to maintain free of defects.

Dual bus adaptable data path interface system

A dual bus interface module, providing communication between a processor means and/or translation logic means and a set of dual system busses, provides a programmable transmit logic means which enables bus access for data transfer of commands and message transfer requests to destination modules on said system busses in a manner so as to use any available system bus to complete data transfer requests or to report the status of non-completed requests.

Transmission logic apparatus for dual bus network

An error logging system where errors are captured on dual system busses operating at a lower clock rate (16 MHz) than the processor which receives the error information. The system functions to substantially reduce the loads on the processor in addition to maximizing the use of the system bus drivers which are pin-constrained. The processor operates at a higher clock rate (32 MHz). Processor commands to read error data from an error log register are synchronized down to the 16 MHz rate, then enabled onto a processor bus after a second synchronization operation back to the higher (32 MHz) rate. Provision is made for identifying several different types of error categories. An expandable error log register system is provided which uses selected bit positions to identify types of errors logged to the processor which also enables expansitivity for adding in future types of errors into the error logging system and renders compatibility for a processor operating at first clock rate with error data sensed at a second clock rate.

Error logging system with clock rate translation

A programmable timing logic system for enabling access to a first or second bus, of dual system busses, by a central processor and/or a protocol-timing translation logic unit wherein messages may be received from one bus while command/control data is being transmitted to the other bus. Incomplete command cycles are retried a specific number 'n' of times, each for a preset predetermined time period of 'p' microseconds.

Programmable timing logic system for dual bus interface

A message transfer system between digital modules where two or more digital modules operate on separate and different message lengths and clock frequencies and where, temporary storage buffer (translator unit) holds messages being transferred between the different digital modules and acts as a speed matching and word length matching buffer unit to permit compatible transfer of message words. Also, the transfer system recognizes when requests are outstanding from both digital modules and can discard a message from a requesting module. Each of the two or more separate digital modules is serviced by dual system busses providing for redundancy of data transfer operations.

Translator system for message transfers between digital units operating

A system for controlling and routing messages and data received from dual system busses, through a bus interface unit, to a protocol translation logic means and to a processor in a central processing module connected onto a dual system bus network. The processor operates at a first clock rate and on a single-word communication protocol while the translation logic means operates at a second rate and multiple-word communication protocol. The processor and translation logic are destination modules which receive the benefit of the receiving control logic system. The receiving control logic system also services external modules on the system bus in order to receive data and control the routing of data to the destination modules. Destination modules which are busy and not ready will cause the system to inform the external transmitting modules that they must retry their transmission. The system also checks the quality of the data on the system busses and informs the processor when errors have been incurred, in addition to informing the originating modules when a transmitted message has been completed.

Receiving control logic system for dual bus network

A bus interface transfer system enables communication to/from dual busses to multiple resource units which include a central processor module and a translation logic unit which permits data transfer between systems having different protocols and different clock rates.

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Laguna Niguel, CA, United States of America

Wayne C Datwyler