International Business Machines Corporation

Intel Corporation

Wayne Alan Downer

Thomas D Lovett

Bruce Michael Gilbert

Mehul M Shah

Donald R DeSota

D Scott Guthridge

Gerrit Huizenga

Glenn J Hinton

Raj K Ramanujan

David Zimmerman

Robert S Chappell

Michael A Parker

Rajesh S Parthasarathy

Mario Flajslik

Adrian C Moga

Muthukumar Swaminathan

Thomas Benjamin Berg

Robert Joersz

Eric R Borch

Larry O Smith

Madhavan Parthasarathy

Steven R Carbonari

Scott J Cape

Richard Lindsley

Thomas E Kloos

Richard L Stout

Chandrasekhar Pulamarasetti

Kyle Gerhard Grieser

Technologies for a system of communicatively coupled network switches in a hierarchical interconnect network topology include two or more groups that each include two or more first and second level switches in which each of the first level switches are communicatively coupled to each of the plurality of second level switches to form a complete bipartite graph. Additionally, each of the groups is interconnected to each of the other groups via a corresponding global link connecting a second level switch of one group to a corresponding second level switch of another group. Further, each of the first level switches are communicatively coupled to one or more computing nodes. Other embodiments are described herein.

Technologies for scalable hierarchical interconnect topologies

In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.

Apparatus, method, and system for implementing micro page tables

Partitioning a node of a multi-node system into more than one partition is disclosed. First resources of the node are physically partitioned into more than one partition. The first resources physically partitioned to each partition are directly inaccessible by other partitions of the node. Second resources of the node are then internally logically partitioned into the more than one partition. Each second resource internally separates transactions of one partition from transactions of other partitions. Furthermore, the node can be dynamically repartitioned into other partitions, such as a single partition, without having to take the multi-node system down. Operating system (OS) instances of the partitions may have assumptions provided to allow for dynamic partitioning, such as quiescing the processors and/or the input/output components being reconfigured, purging remote cache entries across the entire OS, etc. Each partition may have associated therewith registers that are protected from access by other partitions.

Partitioning of node into more than one partition

Employing a coherency controller having a primary path and at least one secondary path to at least one interconnection network is disclosed. A method of an embodiment of the invention is performed by the coherency controller of a node. The coherency controller determines whether transactions are being properly sent to other nodes of a plurality of nodes of which the node is a part via a primary path. In response to determining that the transactions are not being properly sent to the at least one interconnection network via the primary path, the coherency controller instead sends the transactions to the other nodes via a secondary path.

Secondary path for coherency controller to interconnection network(s)

The management of transactions received by a coherency controller is disclosed. A method of an embodiment of the invention is performed by a coherency controller of a plurality of coherency controllers of a node that has a plurality of sub-nodes. The coherency controller receives a transaction from one of the sub-nodes of the node. The transaction may relate to another sub-node of the node. However, the coherency controller nevertheless processes the transaction without having to send the transaction to another coherency controller of the node, even though the sub-node from which the transaction was received is different than the sub-node to which the transaction relates. The plurality of coherency controllers is thus shared by all of the plurality of sub-nodes of the node.

Coherency controller management of transactions

A masterless approach binds multiprocessor building blocks to partitions of a computer system using identifiers and indicators. A number of building blocks communicate among each other to determine a partition to which each building block is to be partitioned. For each unique partition to which one or more of the building blocks is to be partitioned, the building blocks communicate among each other to determine building block uniqueness, and then each of the building blocks joins the partition. The building blocks share with one another their logical port identifiers, which uniquely identify the building block within a partition. A commit indicator of each building block indicates that the building block has committed itself to the partition and that its identifiers cannot be changed. A partition protect indicator is set by one building block of a partition, preventing changes to the commit indicators of other building blocks wishing to join the partition except by that one building block, effectively protecting the partition. Building block protect indicators protect the building blocks themselves.

Masterless building block binding to partitions using identifiers and indicators

Removing building blocks from partitions to which they have been bound is disclosed. A building block of a platform is removed from a partition of the platform by first halting activity by the partition on the building block. A first partition identifier of the building block indicates the partition of the building block. The building block joined the partition in a masterless manner. The resources of the building block are withdrawn from the partition, and the building block is deauthorized from the platform.

Building block removal from partitions

A system and method of partitioning a multiprocessor or multinode computer system containing two or more partitions each of which contain at least three nodes or processors and a central hardware device communicating with a requestor node or processor, a target node or processor and at least one additional node or processor in the partition. The multiprocessor system architecture allows for partitioning resources to define separate subsystems capable of running different operating systems simultaneously. The method operates with the central device, a tag and address crossbar system, which transmits requests for data from the requestor node to the target node, but not to any of the additional nodes or processors which are not defined as part of a given partition. The method provides steps of assignment of definitions to physical ports with the central device corresponding with desired partitioning of resources within the system. Data processed within the system is assigned tags which themselves are related to the defined system resources allocated to one or more desired partitions within the system.

Hardware support for partitioning a multiprocessor system to allow distinct operating systems

A masterless approach for binding building blocks to partitions is disclosed. Other blocks are first sent a first physical port identifier indicating a block's physical location, and a first partition identifier indicating the block's partition. Second physical port identifiers and second partition identifiers are received from the other blocks. The first physical port identifier and the second physical port identifiers of a subset of the other blocks are then sent to the subset, the second partition identifiers of the subset being equal to the first partition identifier. The first physical port identifier and the second physical port identifiers of the subset are also received from each block of the subset. A first logical port identifier indicating the block's logical location is sent to the subset, and second logical port identifiers are received from the subset. The block joins the partition indicated by the first partition identifier.

Masterless building block binding to partitions

A means and method to receive and store a continuous flow of data items being processed in a data processing system in which data items are received from multiple sources simultaneously. The invention provided for simultaneous retrieval of previously stored data from multiple destinations while providing low latency of the retrieved data. The invention utilizes multi-port random access memory or register arrays with fewer ports than the number of actual data sources or data destinations within the system. The disclosure teaches a means of providing the control of data flow to multi-port simultaneous access memory systems, utilizing the control paths in the memory control systems rather than the data paths in such systems. The system eliminates or reduces the need for memory buffers to manage data flow into or out of system memory devices which have a limited number of ports or paths connecting system memory to the input and output systems of the data processing system.

Method and apparatus for multi-path data storage and retrieval

Identifying the mounting locations of sub-systems in mounting units, such as rack cabinets, is disclosed. A mounting unit has a number of sub-system mounting locations. Each of one or more sub-systems is mounted in a corresponding sub-system mounting location of the cabinet. Each of one or more active indicators has an indicator mounting position on either the mounting unit or one of the sub-systems. Each of one or more sensors has a sensor mounting position similarly on either the mounting unit or one of the sub-systems, and also detects indication from a corresponding active indicator. The active indicators and the sensors cooperatively function to identify the corresponding sub-system mounting location of each sub-system in the mounting unit.

Identification of mounting locations of sub-systems in mounting units

In a multiprocessor system, a method for dynamically establishing an I/O path between a processor node and an I/O device for routing data there between. The method starts with providing a configuration graph. The graph has objects associated with elements (devices) of the system and links connecting the objects. The node is identified, and links are then followed in the graph from an object associated with the I/O device to an object associated with a node. If multiple I/O paths exist and an optimal path is desired, the method includes providing in the links routing information containing nodes that can be directly reached via the link. Links are then followed, if possible, whose routing information contains the identified node. If no link having such routing information exists at an object along the path, then another link is chosen having routing information containing another node. This other link may be chosen in a round robin manner if there are multiple links to choose from. If multiple links having such routing information exist at an object along the path, then one of the links is chosen in a round robin manner. The method may also be used in uniprocessor systems such as a system with a one-processor node for simply establishing multiple paths to provide fault tolerance.

Method for routing I/O data in a multiprocessor system having a non-uniform memory access architecture

A method for configuring devices within a computer system provides device configuration information for types of devices that may be included within the computer system. The device configuration information for a device type includes interface types by which devices of that device type connect to other devices. The method includes determining the interface types of a current object associated with a device. Device types that can exist on a determined interface type of the current object are probed for. A child object is created for a device found from the probing and a link between the current object and the child object is also created. A child object is then made the current object, and the above actions are repeated at least until the devices to be configured within the system have associated objects linked together.

Dynamic method for configuring a computer system

Computer-based devices, whether initiators or targets, are assured access to a bus having a fixed priority arbitration scheme (such as a SCSI bus) by assigning to each initiator a &ldquo;fair share&rdquo; of the bus bandwidth. This share is defined as a number of bytes per a unit of time such as a time period. The shares together total a fraction of the total bus bandwidth, with a margin of bus bandwidth left unassigned. To prevent initiator starvation, each initiator monitors its bus requests to determine if it is being prevented by higher-priority initiators from using its assigned share of the bandwidth. If not, the initiator periodically pings each higher-priority initiator to indicate that it is not being starved. So long as a higher-priority initiator continues to receive pings from all lower-priority initiators, the higher-priority initiator can continue to use as much bandwidth as it needs. If the higher-priority initiator fails to receive a ping from a lower-priority initiator, it stops sending new bus requests to the SCSI bus, making the bandwidth available to the lower-priority initiator. To prevent target starvation, each initiator monitors its outstanding bus requests to targets. If a request does not complete in an appropriate time, the initiator pings all other initiators with notification of target starvation. In response, all initiators limit their new bus requests to their share of the bandwidth. This limiting makes the unassigned margin of bus bandwidth available to the targets.

Growing community of inventors

Portland, OR, United States of America

Wayne Alan Downer