Sun Microsystems, Inc.

Wayne A Morse

Scott R Nelson

Michael Frank Deering

Kevin C Rushforth

Michael G Lavelle

Brian D Emberling

Nathaniel David Naegle

Ewa M Kubalska

David C Kehlet

Michael Wasserman

Roger Swanson

Huang Pan

Mike Lavelle

Adeleke Ajirotutu

William E Sweeney, Jr

Rangit S Oberoi

Don Peterson

A graphics system comprising a plurality of rendering pipelines and a scheduling network. Each rendering pipeline couples to the scheduling network, and includes a media processor, a rendering unit and a memory. A communication bus may couple the scheduling network and the memory of each rendering pipeline. The media processor in each rendering pipeline may direct the saving of state information of the corresponding rendering pipeline to the corresponding memory in response to receiving a corresponding context switch indication. A first of the media processors initiates the transfer of a resume token to the scheduling network through the corresponding rendering pipeline if the context switch occurs during an ordered processing mode. The scheduling network unblocks one or more rendering pipelines other than the first rendering pipeline in response to receiving the resume token.

Method for context switching a graphics accelerator comprising multiple rendering pipelines

A graphics system configured to apply multiple layers of texture information to primitives. The graphics system receives parameters defining a primitive and performs a size test on the primitive. If the size test cannot guarantee that a fragment size of the primitive is less than or equal to a fragment capacity of a texture accumulation buffer, the primitive is divided into subprimitives, and the graphics system applies the multiple layers of texture to fragments which intersect the primitive. The graphics system switches from a current layer to the layer next when it has applied textures corresponding to the current layer to all the fragments intersecting the primitive. The graphics system stores color values associated with the primitive fragments in the texture accumulation buffer between the application of successive texture layers.

Graphics primitive size estimation and subdivision for use with a texture accumulation buffer

A method and computer graphics system for clip testing using clip bits stored in a general-purpose register for each vertex of a geometric primitive. In one embodiment, a rendering unit or other processor sets bits in a clip bits register for each vertex of a geometric primitive. Each bit indicates whether the vertex is inside or outside of a clipping boundary with respect to a particular clipping plane. A frame buffer controller or other graphics processor performs clip testing on the entire geometric primitive by performing Boolean operations on the clip bits. The frame buffer controller may trivially accept or trivially reject the primitive based on the clip testing. If the primitive cannot be trivially rejected or trivially accepted, then the frame buffer controller sends an interrupt to the rendering unit. The rendering unit reads an exception register to determine that the reason for the interrupt is the need to clip the primitive. The rendering unit reads the vertices from the frame buffer controller, clips the primitive, and sends the new vertices to the frame buffer controller. The frame buffer controller clears the interrupt and resumes its graphics processing.

Graphics system using clip bits to decide acceptance, rejection, clipping

A 3-D graphics accelerator for performing lighting operations using operands within a given fixed point numeric range. The 3-D graphics accelerator includes a first computational unit which is configured to compute a value of an attenuation factor usable for performing said lighting operation for local lights. The attenuation factor is represented in floating point format. The first computational unit is also configured to represent the attenuation factor in an intermediate format including a first intermediate value (a scaled attenuation factor value within the given fixed point numeric range), and a second intermediate value (a shift count usable to convert the scaled attenuation factor value back to the original attenuation factor value). The 3-D graphics accelerator further includes a lighting unit coupled to said first computational unit. The first computational unit is further configured to convey the intermediate representation of the attenuation factor to the lighting unit. The lighting unit performs lighting calculations in fixed point, using operands within the given numeric range (such as the scaled attenuation factors). The lighting unit generates intermediate color values as a result of these lighting calculations. The lighting unit then uses the shift count value to shift the intermediate color values by an appropriate amount, thereby generating a final color value. The lighting unit clamps said final color value to a predetermined maximum color value in response to said final color value exceeding said predetermined maximum color value.

Graphics accelerator with shift count generation for handling potential

A lighting unit for improved processing of multiple light sources. The lighting unit includes an input buffer for receiving one or more attributes corresponding to a given polygon. The lighting unit further includes a first light parameter storage location for storing a first set of light parameters for a first light source illuminating the given polygon, and a second light parameter storage location for storing a second set of light parameters for a second light source illuminating the given polygon. Still further, the lighting unit includes a first light type storage location which stores a lighting routine index for the first light source, and a second light type storage location which stores a lighting routine index for the second light source. The first light type storage location is initialized to be a current light type storage location. The lighting routine indices point to a particular lighting routine to be performed for a given type of light source. The lighting unit finally includes a control unit configured to execute a next light instruction. The next light instruction comprises accessing the current light type storage location to obtain the first lighting routine index. The next light instruction further comprises updating the current light type storage location to be the second light type storage location in preparation for a subsequent execution of the next light instruction. The control unit is further configured to effectuate performing a first lighting routine specified by the first lighting routine index.

Lighting unit for a three-dimensional graphics accelerator with improved

A computer system which exhibits increased performance for stereo viewing. The computer system includes a display screen, a bus for transferring data, a memory coupled to the bus for storing geometric primitives and left and right view transformation matrices. Furthermore, the computer system includes a processor coupled to the bus, wherein the processor is configured to enable stereo mode and to execute an application for rendering objects on the display screen in the stereo mode. The computer system also includes a graphics accelerator coupled to the bus. The graphics accelerator includes a buffer for storing a received geometric primitive to be rendered in stereo mode, as well as memory for storing the left and right view transformation matrices. The graphics accelerator also includes a transformation unit which is configured to generate a first transformed geometric primitive in response to the received geometric primitive and the left view transformation matrices. The transformation unit is configured to subsequently generate a second transformed geometric primitive in response to the received geometric primitive and the right view transformation matrices. The received geometric primitive is maintained in the buffer subsequent to generation of the first transformed geometric primitive at least until accessed by said transformation unit during generation of second transformed geometric primitive.

Floating point processor for a three-dimensional graphics accelerator

A lighting unit which exhibits improved handling of incoming color values corresponding to a polygon. The lighting unit includes an input buffer for storing a plurality of color values, a mode register including a color mode field specifying whether the plurality of color values corresponds to the front or back side of the polygon. Furthermore, the lighting unit includes a register file for storing color information. The register file includes a first and second plurality of registers for storing front and back side color information, respectively. Still further, the lighting unit includes input/output logic configured to perform a transfer color instruction, which first comprises accessing the mode register to obtain a value of the color mode field, and then transferring the plurality of color values from the input buffer to one or more registers within the register file. The one or more registers are located within the first plurality of registers if the value of the color mode field indicates that the plurality of color values correspond to front side color information, and are located within the second plurality of registers if the value of the color mode field indicates back side color information. The one or more registers are located within the first and second plurality of registers if the value of the color mode field indicates both front and back side color information. Finally, the lighting unit includes a lighting computation unit configured to determine a face direction of the polygon. The lighting unit is further configured to use one or more of the plurality of color values (selected in accordance with the face direction) to perform lighting calculations for the polygon.

A floating point processor for a 3-D graphics accelerator which includes improved performance over prior art designs. The floating point processor includes three specialized engines or function units which streamline floating point operations and which provide improved performance over prior systems. In the preferred embodiment, the floating point processor comprises a floating point core (F-core), a lighting core (L-Core), and a set-up core (S-core). Computations for triangles and vectors are split over the three function units for improved efficiency. The F-core processor receives geometry primitive data and performs floating point operations on the received geometry data. The L-Core processor comprises a fixed point computational unit for performing lighting computations. The set-up core comprises a fixed point computational unit for performing set-up calculations for geometric primitives. Therefore, the present invention comprises an improved floating point processor for a three-dimensional graphics accelerator which includes three separate processing units for improved performance.

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Fremont, CA, United States of America

Wayne A Morse