Unisys Corporation

Sperry Corporation

Wayne A Michaelson

Larry L Byers

Joseba M De Subijana

Joseba M Desubijana

Howard A Koehler

James H Scheuneman

Richard F Paul

Howard Huy Tran

Gary R Robeck

Lloyd E Thorsbakken

Steven M Wierdsma

Daniel K Zenk

Joseba A DeSubijana

A micro code operated microsequencer that includes a monitor, a timer, a function controller and an address controller controls the functioning of a number of operational stations which exchange address and data signals with the microsequencer over a bus. The stations have designated tasks to perform and are selectable by the controller. When the station selected performs a task that requires a read from a RAM memory, the microsequencer selects a time-out duration during which the selected station is expected to complete its assigned task which is long enough to take into account the added time needed to perform the read from memory. If the station selected performs a write task, the microsequencer selects a shorter time duration during which the selected station is expected to complete this task since no memory read is needed. If any assigned task exceeds its appropriate time-out duration, an error condition will be sensed and the microsequencer will not receive an active Continue signal from the selected stations as long as their assigned tasks remain uncompleted.

Bus request error detection

An apparatus for efficiently detecting errors in a system having a plurality of memory devices. The present invention uses a single parity bit configuration to detect common data errors caused by faulty memory devices including multiple data errors within one memory device. This is accomplished by effectively turning a multiple bit error detection situation into a single bit error detection situation. Thus, instead of allocating a contiguous block of bits to the same memory unit, the present invention allocates bits across all memory units in a round-robin fashion. The parity domains are defined such that multiple errors within one SRAM can be detected despite only using a single bit parity configuration.

Multiple memory bit/chip failure detection

A system and method for updating partial blocks of file data stored in a non-volatile storage within a file cache system connected to a host computer system. A first buffer and a last buffer receive from the non-volatile storage the existing portions of the blocks that are to be retained. A write buffer receives new data of a size not equal to an integral multiple of a block from a host computer system. The new data is merged under hardware control with the existing portions contained in the first buffer and the last buffer, thereby updating the cached file.

System and method for storing partial blocks of file data in a file

A method and apparatus for executing conditional branch instructions by a data processing system containing a programmable microprocessor and multiple VLSI gate arrays connected by a bi-directional bus, whereby a branch condition is obtained from a storage location resident on a VLSI gate array executing asynchronous and external to the microprocessor. The branch condition is fetched and evaluated in parallel with the fetching of the branch target address and the incrementing of the program counter. The microprocessor changes instruction sequence control depending on the results of the branch condition evaluation.

System and method for processing external conditional branch instructions

A microsequencer bus controller system provides a flexible and efficient mechanism for controlling multiple gate arrays called stations embedded within a larger computer system. A control store memory, loaded at system initialization time, holds fixed-length instructions simultaneously executed by dual reduced instruction set (RISC) microprocessors which interface with the multiple stations over a bi-directional bus. The master microprocessor compares the result of the processing of each instruction with the slave microprocessor's result to detect any differences, thereby minimizing error latency. Master and slave microprocessors each control half of the stations on the bus. Data widths of 32-bit and 36-bit words are supported by the microprocessors, bus, and stations.

Microsequencer bus controller system

A bus architecture includes address lines, data lines, and control signals to allow a processor to communicate with a VLSI gate array. The address lines are interpreted by the VLSI gate array to select either multi-bit registers or single bit designators resident on the VLSI gate array depending on which control signal is received from the processor. Dual address decode logic on the VLSI gate array senses control signals indicating a request to read from a register, write to a register, and set, clear, or test a designator, and decodes the address received to select the appropriate storage location for the requested function.

Processor communications bus having address lines selecting different

A bus architecture and associated circuitry for providing communication between processors and multiple gate arrays whereby the size of the data being transferred may be either full words of 32-bits or 36-bits per word, or half words of 16-bits or 18-bits per word. Parity generation logic operates on the data to be sent over the bus to generate a parity value from the correct data bits depending on the selected data word size. Parity checking logic operates on the data received from the bus to check the parity of the correct data bits depending on the selected data word size.

Multiple width data bus for a microsequencer bus controller system

A method and apparatus for detecting stuck faults in a signal line used to communicate a branch condition for executing conditional branch instructions by a data processing system containing a programmable microprocessor and multiple VLSI gate arrays connected by a bi-directional bus, whereby the branch condition is obtained from a storage location resident on a VLSI gate array executing asynchronous and external to the microprocessor. The branch condition is fetched and evaluated in parallel with the fetching of the branch target address and the incrementing of the program counter. The microprocessor changes instruction sequence control depending on the results of the branch condition evaluation. The branch condition is sent to the microprocessor as a signal pulse for a specified duration at a particular time, rather than by changing the level of the signal, thereby allowing communication of the branch condition over only one signal line but still providing for detection of faults in the VSLI gate array or faults inherent in the signal line.

Stuck fault detection for branch instruction condition signals

A system and method for detecting errors during the storage and retrieval of file information between a file cache system and a host computer system utilizes a block check sequence key as redundant data included in each block of file data transferred. The block check sequence key is generated by key generation logic and accompanies each block of file data stored in the file cache system by the host computer system. The block check sequence key is a compressed representation of the data within the selected block, as well as unique file and block identification information supplied by the requester of the write operation. When the block is retrieved from the file cache system, the system generates a new block check sequence key based on the data within the retrieved block and the unique file and block identification information supplied by the requester of the read operation. Validation logic ensures that if the retrieved key and the newly generated key does not match, an error signal is activated.

Data block check sequence generation and validation in a file cache

A method and system for executing shift, mask, and merge operations on two operands specified by one instruction contains two registers holding operand data and separate shift, mask, and merge logic. A programmer-defined set of mask and merge indicators controls the mask and merge operations. Each mask and merge indicator is represented as a single bit but controls a pair of bits in an operand. If the first operand is selected by the programmer, it is shifted and then masked. The result of the shift and mask operations is merged with the second operand. If the second operand is selected, it is shifted and masked, and the result is merged with the first operand. Final results are stored for processing by subsequent instructions.

System for processing shift, mask, and merge operations in one

A system and method for executing conditional branch instructions by a processor using dynamic branch address tables containing branch target addresses. The branch target addresses are selected by the result of a computation of fields in the branch instruction and an index generated during the execution of previous instructions. The relevant fields include the base address of a branch address table and a mask value. The contents, size, and location of the branch address tables in a random-access-memory local store may be changed during run-time by program control.

System and method for executing branch instructions wherein branch

An address verification system for providing address error detection whether the error originates at the address generation circuitry, the address transmission path, or the address receiving circuitry. Multiple address generation circuits which simultaneously generate equivalent addresses each have associated parity generation circuits to provide parity bits for its associated address. Monitoring for unequal parity bits generated by the multiple parity generation circuits allows detection of address generation errors. Predetermined address parity bits for each potential address to be sent to the address-receiving circuitry are stored at the address-receiving circuitry to be compared to the parity bits issued by the multiple parity generation circuits. The predetermined address parity bits are determined prior to real-time address transmissions of the system, so that manual or automatic verification of the predetermined parity bits can be performed to ensure correctness of the predetermined address parity bits. The use of predetermined address parity bits which are stored at the address-receiving circuitry allows detection of address transmission and address receipt errors. Monitoring circuitry monitors for parity errors so that appropriate action may be taken upon recognition of such parity errors.

Address verification system using parity for transmitting and receiving

A counter system having associated counter error detection circuitry that utilizes the current parity, the previous parity, and a predicted parity for evaluating counter operation is described. In successive count cycles, a predicted parity is utilized, during the next subsequent count cycle is stored in flip-flop as the current parity, and in the next subsequent count cycle is stored a second flip-flop as a previous parity. Circuit are described for performing parity check and parity prediction functions. The previous parity, current parity and predicted parity will not be alike for any binary counter that operates properly. Circuity is described that holds and compares the parity of the Count, the current parity, and the previous parity, during each counter advance cycle and to provide an error signal when the counter is detected to be stuck.

Counter malfunction detection using prior, current and predicted parity

A bus control and error detection system is provided for a bus system in which data and address signals are transferred between a microsequencer and a number of operational stations which are coupled to the bus. Tri-state drivers are employed in the microsequencer and in the stations which are constructed such that two of the three states of these tri-state drivers are utilized to provide the two states of binary logic operation, and the third state is a high impedance state that protects the components that are coupled to the bus during predefined abort condition which are detected in the system. An abort detection circuit is included in each of the operational stations which is coupled to receive control signals from the microsequencer and which is constructed to emit an ABORT signal output to the microsequencer when the control signals indicate that an abort condition has occurred for the associated operational station. The ABORT signal causes the tri-state driver in the microsequencer to switch to its high impedance state and the microsequencer and transmit LOCK BUS signals to all of the operational stations in order to switch their tri-state drivers to their high impedance states.

Bus station abort detection

A system for apportioning serially supplied data among eight contending memory banks tends to equalize usage among the banks despite their arrangement in a predetermined, sequential priority. Each bank has a data hold register, an OR logic gate to generate a request signal whenever its register contains data, and a negative AND gate for enabling the bank for clearing data from its register. All except the lowest priority bank further include a blocking latch and an enabling NOR gate. Each blocking latch is set when its associated bank is enabled, and then inhibits its associated AND gate and each higher priority AND gate, while enabling each lower priority NOR gate. Each enabled NOR gate provides an enabling signal to all lower priority AND gates. When the lowest priority AND gate is enabled by the NOR gates and its request signal, all blocking latches are cleared. The banks thus are utilized in a sequence that is maintained even if one or more banks are bypassed on occasion.

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Circle Pines, MN, United States of America

Wayne A Michaelson