Motorola Corporation

Wayne A Cronin

Kirby F Koetz

Gordon M Grivna

Mark A Durlam

Jonathan K Abrokwah

John Michael Parsey, Jr

Kelly Wayne Kyler

Jaeshin Cho

Francis W Barton, Jr

Donald S Taylor

Brian L Scrivner

A high temperature metallization system for use with a semiconductor device (23). The semiconductor device (23) has a multi-layer metallization system (36). An adhesion layer (37) of the metallization system (36) is formed on a semiconductor substrate (20). A barrier layer (38) that contains a nickel alloy is formed on the adhesion layer (37). A protective layer (39) is formed on the barrier layer (38). The barrier layer (38) inhibits solder components from diffusing toward the semiconductor substrate (20) during high temperature processing.

Semiconductor metallization structure

A metallization system (19) for a semiconductor component (20) includes depositing a dielectric layer (12) over a substrate (10), etching a via (14) in the dielectric layer (12), sputtering a metal layer (17) of aluminum, copper, and tungsten over the dielectric layer (12) and in the via (14), and sputtering a different metal layer (18) of aluminum and copper over the first metal layer (17) and in the via (14). The metallization system (19) reduces the reliability issues associated with electromigration and stress migration while enhancing the ability to fill vias with large aspect ratios.

Method of fabrication of metallization system

A manufacturable III-V semiconductor structure having small geometries is fabricated. A silicon nitride layer is formed on a III-V semiconductor material and a dielectric layer comprised of aluminum is formed on the silicon nitride layer. Another dielectric layer comprised of silicon and oxygen is formed over the dielectric layer comprised of aluminum. The dielectric layer comprised of aluminum acts as an etch stop for the etching of the dielectric layer comprised of silicon and oxygen with a high power reactive ion etch. The dielectric layer comprised of aluminum may then be etched with a wet etchant which does not substantially etch the silicon nitride layer. Damage to the surface of the semiconductor material by exposure to the high power reactive ion etch is prevented by forming the dielectric layer comprised of aluminum between the silicon nitride layer and the dielectric layer comprised of silicon and oxygen.

Method of manufacture of multilayer dielectric on a III-V substrate

A semiconductor material contacting member which greatly reduces potential for semiconductor material breakage is provided. Preferably, the contacting member is a ceramic cylinder (60) which can be used to brace a semiconductor wafer (14) in a wafer station (2) of a sputtering system. The ceramic cylinder has an annular shoulder at one end (68), with a flat outer surface. The flat outer surface contacts the wafer (14) along a line (74). The line contacting surface (74) distributes pressure and heat across the contacting surface. Additionally, the ceramic cylinder (60) is relatively soft, thus avoiding damaging the semiconductor material.

Semiconductor material contacting member

Growing community of inventors

Tempe, AZ, United States of America

Wayne A Cronin