Qualcomm Incorporated

Other

Way-Shing Lee

Douglas Neal Rowitch

Gilbert Christopher Sih

Thunyachate Ekvetchavit

Li Feng Zhang

Henry S Chang

Raghu Narayan Challa

Peter J Black

Reza Shahidi

Inyup Kang

Haitao Zhang

Farrokh Abrishamkar

Serguei A Glazko

Christopher Patrick

Qiuzhen Zou

Francis M Ngai

Deepu John

Ian J Fevrier

Quaeed Motiwala

Randeep Singh

Gil Sih

Chienchung Chang

Sanjay K Jha

De Dzwo Hsu

Xufeng Chen

Jian Lin

Rajiv R Nambiar

John G McDonough

Charles E Sakamaki

Karthick Chinnaswami

George Gaozhi Pan

Prashant A Kantak

Hemant Kumar

Hanchi David Huang

Robert Opalsky

Steven C Den Beste

James A Hutchison

Quizhen Zou

Michael K Spartz

De D Hsu

DSP architectures having improved performance are described. In an exemplary architecture, a DSP includes two MAC units and two ALUs, where one of the ALUs replaces an adder for one of the two MAC units. This DSP may be configured to operate in a dual-MAC/single-ALU configuration, a single-MAC/dual-ALU configuration, or a dual-MAC/dual-ALU configuration. This flexibility allows the DSP to handle various types of signal processing operations and improves utilization of the available hardware. The DSP architectures further includes pipeline registers that break up critical paths and allow operations at a higher clock speed for greater throughput.

Digital signal processors with configurable dual-MAC and dual-ALU

Demodulator architectures for processing a received signal in a wireless communications system. The demodulator includes a number of correlators coupled to a combiner. Each correlator typically receives and despreads input samples (which are generated from the received signal) with a respective despreading sequence to provide despread samples. Each correlator then decovers the despread samples to provide decovered 'half-symbols' and further demodulates the decovered half-symbols with pilot estimates to generate correlated symbols. The decovering is performed with a Walsh symbol having a length (T) that is half the length (2T) of a Walsh symbol used to cover the data symbols in the transmitted signal. The combiner selectively combines correlated symbols from the assigned correlators to provide demodulated symbols. One or more correlators can be assigned to process one or more instances of each transmitted signal. The pilot estimates used within each assigned correlator to demodulate the decovered half-symbols are generated based on the signal instance being processed by that correlator.

Method and apparatus for demodulating signals processed in a transmit diversity mode

A method for overload detection according to one embodiment of the invention includes a control process and a data process. In response to a timing signal, the control process sets a state of a timing indicator. Upon execution of a time-constrained operation, the data process checks the state of the timing indicator. In other embodiments, subsequent to an overload detection, an auxiliary data process is configured to execute in a mode that consumes fewer processing cycles.

System, method, and apparatus for overload detection in real-time data processing applications

An apparatus and method for echo cancellation is presented. The echo canceller comprises an adaptive filter that tracks the impulse response of the echo path and produces an estimate of the echo. Filter adaptation is controlled by a controller based on the rate of the far-end speech signal, the rate of the near-end signal, an acoustic loss measure, and a double talk hangover indicator. The controller may also comprise a step size adaptation unit for determining the adaptation step size of the adaptive filter. In addition, the controller may comprise a noise replacement unit, which controls replacement of the echo residual signal with comfort noise to ensure echo is completely rejected when only the far-end speaker is talking.

Acoustic echo canceller

A spread spectrum wireless device ( ) may include a receiver ( ), a searcher ( ), a search controller ( ) and other features. The search controller ( ) selectively generates control signals to control the searcher ( ), which searches for a spread-spectrum signal. In one embodiment, the architecture of the searcher ( ) is dynamically configurable by the search controller ( ) to selectively search multiple channels using multiple frequency bins for the signal.

System and method for acquiring a received signal in a spread spectrum device

Demodulator architectures for processing a received signal in a wireless communications system. The demodulator includes a number of correlators coupled to a combiner. Each correlator typically receives and despreads input samples (which are generated from the received signal) with a respective despreading sequence to provide despread samples. Each correlator then decovers the despread samples to provide decovered &ldquo;half-symbols&rdquo; and further demodulates the decovered half-symbols with pilot estimates to generate correlated symbols. The decovering is performed with a Walsh symbol having a length (T) that is half the length (2T) of a Walsh symbol used to cover the data symbols in the transmitted signal. The combiner selectively combines correlated symbols from the assigned correlators to provide demodulated symbols. One or more correlators can be assigned to process one or more instances of each transmitted signal. The pilot estimates used within each assigned correlator to demodulate the decovered half-symbols are generated based on the signal instance being processed by that correlator.

A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories. An instruction decoder decodes the instructions from the instruction memory and generates control signals that cause data to be exchanged between the various registers, data memories, and functional units, allowing multiple operations to be performed during each clock cycle.

Multiple-data bus architecture for a digital signal processor using variable-length instruction set with single instruction simultaneous control

The invention is a digital signal processor architecture that is designed to speed up frequently-used signal processing computations, such as FIR filters, correlations, FFTs, and DFTs. The architecture uses a coupled dual-MAC architecture (MAC ), (MAC ) and attaches a dual-MAC coprocessor (MAC ), (MAC ) onto it in a unique way to achieve a significant increase in processing capability.

DSP with dual-mac processor and dual-mac coprocessor

A hands free telephone system includes a telephone having audio circuits for processing an audio signal and a telephone audio connector for transmitting the audio signal between the audio circuits and the telephone audio connector. A telephone holder has a holder program for instructing the telephone holder to perform telephone functions in accordance with the stored program. A method for programming a telephone that includes transmitting a plurality of programming instructions between the programming device and the telephone holder, each programming instruction corresponding to a memory location within the holder memory, determining whether the transmitted programming instructions correspond to adjacent memory locations within the telephone holder, and determining an error condition in accordance with determination of whether the transmitted programming instructions correspond to adjacent memory locations.

Programmable hands free telephone system

The present invention is a novel and improved method and circuit for digital signal processing. One aspect of the invention calls for the use of a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. Furthermore, additional aspects of the invention are realized by having instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. Thus, multiple operations are performed during each clock cycle, reducing the total number of clock cycles necessary to perform a task. The exemplary DSP includes a set of three data buses over which data may be exchanged with a register bank and three data memories. The use of more than two data buses, and especially three data buses, realizes another aspect of the invention, which is significantly reduced bus contention. One embodiment of the invention calls for the data buses to include one wide bus and two narrow buses. The wide bus is coupled to a wide data memory and the two narrow buses are coupled to two narrow data memories. Another aspect of the invention is realized by the use of a register bank that has registers accessible by at least two processing units. This allows multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. The processing units in the exemplary embodiment of the invention include an arithmetic logic (ALU) and a multiply-accumulate (MAC) unit. When combined with the use of the multiple bus architecture, highly parallel instructions, or both, an additional aspect of the invention is realized where highly pipelined, multi-operation, processing is performed.

Variable length instruction decoder

A method and apparatus for communicating both voice and control data between a communication device (such as a cellular phone) and an external accessory (such as a hands-free kit) over a data bus. The method includes formatting a sequence of bits into a repeating sequence of first time slots and second time slots, transmitting the voice data in the first time slot, and transmitting the control data in the second time slot. Notably, a first bit of each of the second time slots comprises a clock bit that alternates between a high value and a low value (e.g. a '1' or a '0') as between consecutive second time slots.

Communication protocol between a communication device and an external accessory

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San Diego, CA, United States of America

Way-Shing Lee