United Microelectronics Corp.

Other

United Semiconductor Corp.

United Silicon Incorporated

United Integrated Circuits Corp.

Water Lur

Juan-Yuan Wu

Shih-Wei Sun

Tri-Rung Yew

Coming Chen

Chih-Chien Liu

Tony Lin

Ming-Sheng Yang

Gwo-Shii Yang

David Lee

Cheng H Huang

J Y Wu

Jiun Y Wu

Kuang-Chih Wang

Jiunn Y Wu

Kuo-Tai Huang

Wen-Yi Hsieh

Yimin Huang

Cheng-Han Huang

Ta-Shan Tseng

Anna Su

Edward Houn

Wen-Bin Shieh

Hsueh-Chung Chen

Hsueh-Hao Shih

Jenn-Tarng Lin

Ben Chen

Jiunn-Yuan Wu

Der Yuan Wu

Joey Lai

Chen-Chiu Hsue

Jemmy Wen

Joe Ko

Cheng-Yuan Tsai

Kun-Chih Wang

Jenn Tsao

Chao-Yuan Huang

Fu-Tai Liou

Hsien-Ta Chung

Shih-Chanh Chang

Po-Wen Yen

D Y Wu

Kuen-Jian Chen

Cheng-Hen Huang

Jiunh-Yuan Wu

Neng H Shen

Ting-Chang Chang

Ming-Tzong Yang

Kuan-Cheng Su

Hua-Chou Tseng

Po-Tsun Liu

Chih-Hsiang Hsiao

Der-Yuan Wu

Meng-Jin Tsai

Mu-Chun Wang

Hong-Tsz Pan

Chih-Yung Lin

Meng-Chang Liu

Chiung-Sheng Hsiung

Ming-Tsung Liu

Nien-Tsu Peng

Tsang-Jung Lin

Hong J Wu

Peter Y Lin

Kevin Hsieh

Lawrence Y Lin

Jiun-Yuan Wu

Her-Song Liaw

Chin-Lai Chen

Shim F Tzou

Liang-Chih Lin

Paul P Yen

Hsiaw-Sheng Chin

Chang-Shyan Kao

Dey Y Wu

Yu-Min Dang

Johnson Liu

Pin-Iuh Chen

Yu-Hao Chen

Peter Chang

Shin-Wei Sun

Gwo-Shii Yong

Wen Bin Shieh

W B Shieh

Hsiao-Lin Lu

Chung-Shien Kao, Deceased

Chen H Huang

A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

High density plasma chemical vapor deposition process

An air gap structure and formation method for substantially reducing capacitance in a dual damascene based interconnect structure is disclosed. The air gap extends above, and may also additionally extend below, the damascene interconnects desired to be isolated thus minimizing fringing fields between the lines. Multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels.

Air gap for dual damascene applications

An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.

Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit

An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with either damascene or conventional integrated circuit metallization schemes. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.

Air gap formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device

An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with a tungsten plug process. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.

Air gap for tungsten/aluminum plug applications

A semiconductor substrate is provided, and at least one first mask is formed above the semiconductor substrate. The first mask has a plurality of thicknesses and blocks at least one semi-insulating region. A second mask is thereafter formed on a surface of the semiconductor substrate. The second mask covers the semi-insulating region. The semi-insulating region is implanted with a high energy beam of particles by utilizing the second mask and the first mask as particle hindering masks. Finally, the second mask is removed.

Method of forming a semi-insulating region

A semiconductor substrate is provided, and at least one first mask is formed above the semiconductor substrate. The first mask blocks at least one semi-insulating region. A second mask is thereafter formed on a surface of the semiconductor substrate. The second mask covers the semi-insulating region. The semi-insulating region is implanted with a high energy beam of particles by utilizing the second mask and the first mask as particle hindering masks. Finally, the second mask is removed.

A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is formed. A number of shallow trenches are formed between the active regions one or more of which may constitute an alignment mark. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask exposes a portion of the oxide layer over the large active area and over the alignment mark. The oxide layer of each large active region and the alignment mark is removed. The partial reverse active mask is removed. The oxide layer is planarized.

Chemical mechanical polishing in forming semiconductor device

A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relatively small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask has an opening at a central part of each relatively large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

Chemical mechanical polishing for forming a shallow trench isolation structure

A method of forming a partial reverse active mask. A mask pattern comprising a large active region pattern with an original dimension and a small active region pattern is provided. The large active region pattern and the small active region pattern are shrunk until the small active region pattern disappears. The large active region pattern enlarged to a dimension slightly smaller than the original dimension.

Method of forming partial reverse active mask

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Taipei, Taiwan

Water Lur