Fujitsu Corporation

Fujitsu Microelectronics Limited

Wataru Yokozeki

Hiroshi Shimizu

Shoichi Masui

Tetsuo Ashizawa

Kazuto Furumochi

Akio Itoh

Kenji Mukaida

Michiya Oura

Tsuzumi Ninomiya

A frequency comparator compares frequencies of a reference clock and an output clock to output a frequency comparison signal. A frequency variable circuit is composed of a delay circuit, which has a plurality of inverting circuits connected in series, and a first selection circuit. The first selection circuit selects one of odd output signals outputted from odd-numbered inverting circuits, according to the frequency comparison signal to feedback the selected odd output signal to an input of the delay circuit as a feedback signal. A phase comparator compares phases of the reference clock and the output clock to output a phase comparison signal. A second selection circuit selects one of the odd output signals according to the phase comparison signal to output it as the output clock.

Digital PLL circuit

A semiconductor memory device that speeds up its operation. A multiplexer puts one of word lines into an active state to select one memory cell in each local block. Another multiplexer puts one of local block selection signals into an active state and puts one of p-channel transistors into the ON state to select one of local blocks arranged in a column direction. A NAND element inverts the logical product of a signal output from a local block selected by a local block selection signal and a signal output from a block not selected and outputs a result obtained to put an n-channel transistor into the ON or OFF state. The n-channel transistor grounds a common bit line when it goes into the ON state. Each of the p-channel transistors is selected by a column switch (not shown) and send read data to a data bus.

Semiconductor memory device

An integrated circuit has a sleep switch, provided between a first power line and a second power line, which is constituted by a transistor of a first threshold voltage, and which becomes non-conducting in a sleep mode, and further has a latch circuit, connected to the second power line, which is constituted by a transistor of a second threshold voltage which is lower than the first threshold voltage, and a ferroelectric capacitor for storing data held in the latch circuit in accordance with the polarization direction of a ferroelectric film thereof. The integrated circuit also comprises a control signal generating circuit which, when returning to an active mode from the sleep mode, generates a plate signal for driving a terminal of the ferroelectric capacitor to generate a voltage in the latch circuit in accordance with the polarization direction, and generates a sleep signal for causing the sleep switch to conduct to thereby activate the latch circuit following the driving of the ferroelectric capacitor.

Multi-threshold-voltage integrated circuit having a non-volatile data storage circuit

At switching normal operation mode to low power mode, a first switch disconnects a virtual power supply line and a normal power supply line in response to activation of a switch control signal. The power supply voltage to a first circuit block connected to the virtual power supply line is suspended during the low power mode. A second switch of a floating prevention circuit connects a node between output of the first circuit block and input of a second circuit block to a first voltage line in response to inactivation of the switch control signal during the low power mode. This prevents the input of the second circuit block from floating even without the power supply voltage supplied to the first circuit block, and therefore prevents feedthrough current from flowing through the second circuit block, which enables reduction in power consumption during the low power mode.

Semiconductor integrated circuit

A nonvolatile data storage circuit has a data holding circuit having a storage node, and a plurality of ferroelectric capacitors one electrodes of which are connected to the storage node. In this nonvolatile data storage circuit, in store operations to write data from the data holding circuit to the ferroelectric capacitors, the timing of at least the rising or the falling of plate signals supplied to the other electrodes of the plurality of ferroelectric capacitors, is made different. During store operation, the timing of the plate signals applied to the plurality of ferroelectric capacitors connected to the storage node is shifted, so that coupling noise between the ferroelectric capacitors is dispersed and can be reduced, and data inversion of the data holding circuit can be prevented.

Nonvolatile data storage circuit using ferroelectric capacitors

A nonvolatile semiconductor memory device includes a substrate, a plurality of transistors formed on the substrate to constitute a latch, a plate line, and a pair of capacitors each including a lower electrode, a ferroelectric film, and an upper electrode, the pair of capacitors being provided in a layer situated above the substrate and below a metal wiring layer in which the plate line is formed.

Nonvolatile semiconductor memory device with stable ferroelectric capacitor

A programmable logic device with ferroelectric configuration memories storing multiple configuration data sets. The device has programmable logic blocks, interconnections, and I/O blocks to provide desired logic functions. Those building blocks can be dynamically reconfigured by changing the selection of configuration data stored in the device's integral configuration memories. The configuration memories are divided into groups, so that they can be loaded concurrently with multiple configuration data streams. To protect the content of configuration memories from unauthorized access, the device employs an authentication mechanism that uses security IDs stored in the configuration memories. The device has a memory controller to provide an appropriate power supply sequence for ferroelectric memory cells to ensure the reliable data retention when the device is powered up or shut down.

Programmable logic device with ferroelectric configuration memories

First buffers of a first driver circuit generate voltages to be supplied to word lines, respectively. Second buffers of a second driver circuit operate in synchronization with the first buffers to generate voltages to be supplied to first substrate lines, respectively. Each second buffer, upon access to memory cells, supplies a voltage for lowering the threshold values of transfer transistors and driver transistors to its corresponding first substrate line, and supplies thereto a voltage for raising the threshold values of the transfer transistors and the driver transistors during standby. This can improve the operation speed at the time of accessing the memory cells and reduce the leak current during standby. This results in shortening the access time during the operation of the semiconductor memory and reducing the standby current during standby.

Semiconductor memory

A semiconductor memory device comprises a memory cell array, a decoder unit selecting a word line of the memory cell array, a first dummy cell array connected to a first dummy bit line and disposed with the memory cell array at a first location away from the decoder unit along the word line, a second dummy cell array connected to second dummy bit lines and disposed with the memory cell array at a second location away from the decoder unit along the word line, the second location being farther from the decoder unit than the first location, and a timing control unit determining timing of activation and deactivation of an internal control signal.

Semiconductor memory having a plurality of word lines shared by adjacent local block

A semiconductor device that includes macro cells and a fuse of smaller size. Each macro cell includes normal blocks and a redundant block. Each normal block includes circuits each having a predetermined function. The redundant block has the same function as the normal blocks have. If one of the normal blocks does not work well, it will be replaced with the redundant block. The fuse holds information for specifying the normal block to be replaced with the redundant block included in the macro cell. This fuse is shared by a plurality of macro cells.

Semiconductor device

A semiconductor memory that reduces the amount of power consumed by an entire unit by decreasing a charging/discharging current. A row direction selection circuit selects predetermined memory cell groups in a row direction in response to a row input address signal. A column direction selection circuit selects predetermined memory cell groups in a column direction in response to a column input address signal. Connection-disconnection circuits connect a divided bit line corresponding to a column selected by the column direction selection circuit of divided bit lines connected to memory cell groups, respectively, selected by the row direction selection circuit to the corresponding common bit line and do not connect divided bit lines corresponding to the other columns.

A semiconductor memory device has a dummy bit line, a reference voltage generating circuit, a comparator circuit, and a timing signal generating circuit. The dummy bit line has a load equal to a load of a bit line, and the reference voltage generating circuit generates a reference voltage. The comparator circuit compares a potential of the dummy bit line with the reference voltage, and the timing signal generating circuit generates various kinds of timing signals based on an output of the comparator circuit. The semiconductor memory device simultaneously selects a plurality of dummy memory cells and connects the selected dummy memory cells to the dummy bit line, and adjusts the potential of the dummy bit line.

Semiconductor memory device with improved operation margin and increasing operation speed regardless of variations in semiconductor manufacturing processes

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Kawasaki, Japan

Wataru Yokozeki