Semiconductor Energy Laboratory Co., Ltd.

Wataru Uesugi

Atsuo Isobe

Tatsuya Onuki

Hikaru Tamura

Kiyoshi Kato

Takahiko Ishizu

Yukio Maehashi

Takuro Ohmaru

Naoaki Tsutsui

Seiichi Yoneda

Takeshi Osada

Tomoaki Atsumi

Hidetomo Kobayashi

A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

Logic circuit, processing unit, electronic component, and electronic device

A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL.

Semiconductor device with stacked structure of memory cells over sensing amplifiers, circuit board and electronic device

A semiconductor device with lower power consumption and an electronic device including the same are provided. To reduce leakage current flowing in a word line driver circuit, a switching element is provided, specifically, between the word line driver circuit and a high or low voltage power source. When there is no memory access, the switching element is turned off, thereby interrupting application of voltage (or current) from the high or low voltage power source to the word line driver circuit. Furthermore, to reduce the stand-by power due to precharge of a bit line, a switching element is provided in a bit line driver circuit, specifically, between the bit line and a high or low voltage power source. When there is no memory access, the switching element is turned off, thereby interrupting application of voltage (or current) from the high or low voltage power source to the bit line driver circuit.

Word line driver comprising NAND circuit

The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors. The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor. The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit. Clock signals whose phases are inverted from each other are input to gates of the first and second transistors. Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit.

Storage circuit and semiconductor device

A semiconductor device including a memory which can perform a pipeline operation is provided. The semiconductor device includes a processor core, a bus, and a memory section. The memory section includes a first memory. The first memory includes a plurality of local arrays. The local array includes a sense amplifier array and a local cell array stacked thereover. The local cell array is provided a memory cell including one transistor and one capacitor. The transistor is preferably an oxide semiconductor transistor. The first memory is configured to generate a wait signal. The wait signal is generated when a request for writing data to the same local array is received over two successive clock cycles from the processor core. The wait signal is sent to the processor core via the bus. The processor core stands by for a request for the memory section on the basis of the wait signal.

Semiconductor device, electronic component, and electronic device

A level-shift circuit that operates stably is provided. The level-shift circuit has a function of boosting a first signal having an amplitude voltage between a first voltage and a second voltage to a second signal having an amplitude voltage between a third voltage and the second voltage. The level-shift circuit includes first to eighth transistors. Gates of the third and seventh transistors are electrically connected to a wiring for transmitting a third signal for controlling the amounts of current flowing into one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, one of a source and a drain of the fifth transistor, and one of a source and a drain of the sixth transistor.

Level-shift circuit, driver IC, and electronic device

A semiconductor device including a register controller and a processor which includes a register is provided. The register includes a first circuit and a second circuit which includes a plurality of memory portions. The first circuit and the plurality of memory portions can store data by an arithmetic process of the processor. Which of the plurality of memory portions the data is stored in depends on a routine by which the data is processed. The register controller switches the routine in response to an interrupt signal. The register controller can make any one of the plurality of memory portions which corresponds to the routine store the data in the first circuit every time the routine is switched. The register controller can make data stored in any one of the plurality of memory portions which corresponds to the routine be stored in the first circuit every time the routine is switched.

Semiconductor device and electronic device

Provided is a semiconductor device having a memory cell array, which is capable of existing in three power-gating states depending on a non-access period to the memory cell array. The memory cell array includes a plurality of memory cells which each have an SRAM and a nonvolatile memory portion having a transistor with an oxide semiconductor in a channel region. The three power-gating states includes: a first state in which a power-gating to the memory cell array is performed; a second state in which the power-gating is performed on the memory cell array and peripheral circuits which control the memory cell array; and a third state in which, in addition to the memory cell array and the peripheral circuits, a power supply voltage supplying circuit is subjected to the power gating.

Semiconductor device with stacked structure of memory cells over sensing amplifiers, circuit board, and electronic device

To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an SRAM provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions. The first data holding portion is electrically connected to the fourth data holding portion through a transistor. The second data holding portion is electrically connected to the third data holding portion through a transistor. While the SRAM holds data, the transistor is on so that both the SRAM and the non-volatile memory hold the data. Then, the transistor is turned off before supply of power is stopped, so that the data becomes non-volatile.

Growing community of inventors

Kanagawa, Japan

Wataru Uesugi