Kabushiki Kaisha Toshiba

Wataru Sekine

Wataru Saito

Syotaro Ono

Hiroshi Ohta

Masaru Izumisawa

Yasuto Sumi

Masakatsu Takashita

Nana Hatano

Miho Watanabe

Munehisa Yabuzaki

Kiyoshi Kimura

Yauto Sumi

Shoichiro Kurushima

According to one embodiment, a power semiconductor device includes a first semiconductor layer, and first, second and third semiconductor regions. The first semiconductor layer has a first conductivity type. The first semiconductor regions have a second conductivity type, and are formed with periodicity in a lateral direction in a second semiconductor layer of the first conductivity type. The second semiconductor layer is provided on a major surface of the first semiconductor layer in a device portion with a main current path formed in a vertical direction generally perpendicular to the major surface and in a terminal portion provided around the device portion. The second semiconductor region has the first conductivity type and is a portion of the second semiconductor layer sandwiched between adjacent ones of the first semiconductor regions. The third semiconductor regions have the second conductivity type and are provided below the first semiconductor regions in the terminal portion.

Power semiconductor device and method for manufacturing same

A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer provided in an upper portion of the first semiconductor layer and alternately arranged parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on the third semiconductor layer; a fifth semiconductor layer selectively formed in an upper surface of each of the fourth semiconductor layers; a control electrode; a gate insulating film; a first main electrode provided on a lower surface of the first semiconductor layer; and a second main electrode provided on the fourth and the fifth semiconductor layers. Sum of the amount of impurities in the second semiconductor layer and the amount of impurities in the third semiconductor layer at an end on the second main electrode side of the second semiconductor layer and the third semiconductor layer is smaller than the sum at a center of the second semiconductor layer and the third semiconductor layer in the direction from the first main electrode to the second main electrode.

Power semiconductor device

A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part. The device includes a first semiconductor layer, and second and third semiconductor layers formed on the first semiconductor layer, and alternately arranged along a direction parallel to a surface of the first semiconductor layer, wherein the device part is provided with a first region and a second region, each of which includes at least one of the second semiconductor layers and at least one of the third semiconductor layers, and with regard to a difference value &#x394;N (=N&#x2212;N) obtained by subtracting an impurity amount Nper unit length of each of the third semiconductor layers from an impurity amount Nper unit length of each of the second semiconductor layers, a difference value &#x394;Nwhich is the difference value &#x394;N in the first region of the device part, a difference value &#x394;Nwhich is the difference value &#x394;N in the second region of the device part, and a difference value &#x394;Nwhich is the difference value &#x394;N in the terminal part satisfy a relationship of &#x394;N&#x3e;&#x394;N&#x3e;&#x394;N.

A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.

Semiconductor device having a junction of P type pillar region and N type pillar region

A semiconductor device includes an n+ type semiconductor substrateand a super junction region that has, on the top of the substrate, an n and p type pillar regionsandprovided alternately. The device also includes, in the top surface of the super junction region, a p type base regionand an n type source layer. The device also includes a gate electrodeon the regionand layervia a gate-insulating film, a drain electrodeon the bottom of the substrate, and a source electrodeon the top of the substrate. In the top surface of the super junction region in the terminal region, a RESURF regionis formed. The RESURF region has a comb-like planar shape with repeatedly-formed teeth having tips facing the end portion of the terminal region.

Semiconductor device including a resurf region with forward tapered teeth

A semiconductor device includes a super junction region that has a first-conductivity-type first semiconductor pillar region and a second-conductivity-type second semiconductor pillar region alternately provided on the semiconductor substrate. The first semiconductor pillar region and the second semiconductor pillar region in a termination region have a lamination form resulting from alternate lamination of the first semiconductor pillar region and the second semiconductor pillar region on the top surface of the semiconductor substrate. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region exhibit an impurity concentration distribution such that a plurality of impurity concentration peaks appear periodically. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region have an impurity amount such that it becomes smaller as being closer to the circumference of the corner part.

Semiconductor device and method of manufacturing the same

Semiconductor device having superjunction structure formed of p-type and n-type pillar regions

A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer provided on a major surface of the first semiconductor layer, a third semiconductor layer provided on the major surface and being adjacent to the second semiconductor layer, a termination semiconductor layer provided on the major surface of the first semiconductor layer in a termination region outside the device region, a channel stop layer, and a channel stop electrode. The channel stop layer is provided in contact with the termination semiconductor layer on the major surface of the first semiconductor layer in an outermost peripheral portion outside the termination semiconductor layer and has a higher impurity concentration than the termination semiconductor layer. The channel stop electrode is provided on at least part of a surface of the channel stop layer and projects toward the termination semiconductor layer beyond at least a superficial portion of the channel stop layer.

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Hyogo-ken, Japan

Wataru Sekine