Canon Kabushiki Kaisha

Wataru Ochiai

Daisuke Shiraishi

Makoto Fujiwara

Akihiro Takamura

Yasuhiro Kato

Masayuki Odagawa

A memory controller comprises a holding unit that holds a plurality of memory accesses to a memory that operates with a first clock. The memory controller generates a plurality of command requests for causing the memory to operate based on the plurality of memory accesses; determines, in synchronization with a second clock having a lower frequency than the first clock, whether a plurality of commands corresponding to the plurality of command requests are issuable, based on a constraint on issuance timings that are respectively set for the plurality of commands; selects, in synchronization with the second clock, one command to be issued to the memory from among commands that have been determined by the determining unit to be issuable; and outputs the selected one command to the memory in synchronization with the first clock.

Memory controller and control method therefor

A memory controller for controlling DRAM, comprising: a first storage unit configured to store requests that each comprise information about a priority and an access type received by the memory controller; a first control unit configured to select requests from the requests; a second storage unit configured to store the selected requests; and a second control unit configured to rearrange the requests stored in the second storage unit to generate a DRAM command and to issue the DRAM command to the DRAM, wherein the second control unit generates a priority access type indicating which access type request to preferentially issue to the DRAM, and the first control unit selects the requests, based on the information about the priority and the access type of each of the requests stored in the first storage unit, and the priority access type.

Memory controller, control method of memory controller, and storage medium

A memory control apparatus configured to access a memory that involves synchronization of a clock signal for command transfer and a clock signal for data transfer with each other, the clock signal for command transfer and the clock signal for data transfer being independent of each other, includes an output unit configured to change an output mode of the clock signal for data transfer based on a memory access state and to output the clock signal for data transfer to the memory based on the output mode.

Memory control apparatus, method for controlling memory control apparatus, and storage medium

A memory control circuit is configured to access a memory including a plurality of banks. The memory control circuit comprises: a holding unit configured to hold an access request from an external circuit; a management unit configured to manage states of the plurality of banks; a determination unit configured to determine, based on an access type of an access request held in the holding unit and the states of the plurality of banks, which access type of command issuance that is read or write is to be prioritized; and an issuance unit configured to issue a command of an access request corresponding to the access type determined to be prioritized by the determination unit, among the access requests held in the holding unit.

Memory control circuit and method for controlling the same

A bus system comprises a master, a first slave, a second slave, and a bus. The master is configured to be able to issue a second request to the second slave after issuing a first request to the first slave and before receiving a response to the first request. The bus comprises: a determination unit configured to, upon receiving the second request, determine whether to permit a transfer of the second request to the second slave; and a suspending unit configured to suspend the transfer of the second request to the second slave while it is determined by the determination unit that the transfer is not permitted. The determination unit determines whether or not the transfer is permitted based on a notification from the first slave regarding processing of the first request.

Bus system permitting parallel access by a master to a plurality of slaves and method of controlling the same

Provided is a controller which issues a first write command for writing all data of a burst access operation on a memory and a second write command for writing data of a burst access operation on a memory per byte. The controller includes a holding unit configured to hold a plurality of commands requesting access to the memory and a selection unit configured to select, in a case where the holding unit holds the second write command and a command that causes a first time penalty longer than a second time penalty needed between the first write command that is issued first and the second write command that is issued next, the second write command prior to the command.

Memory controller and control method thereof

A semiconductor chip transmits a request signal which requests notification of the setting state of a chip identifier to another semiconductor chip connected to one of the upstream and downstream, receives a response signal indicating the setting state of the chip identifier and the value of the chip identifier, as a response to the request signal, and performs a chip identifier setting process based on the response signal. When receiving a request signal from another semiconductor chip connected to the other of the upstream and downstream, the semiconductor chip transmits a response signal indicating the setting state of the chip identifier and the value of the chip identifier, as a response to the request signal.

Semiconductor device and chip identifier setting method

A memory control circuit is configured to take a priority for each transfer instruction into account but not the priority in a memory access unit, and thus processing of a high-priority transfer instruction received during a memory access needs to wait for a long time. The memory control apparatus divides the received transfer instruction into a memory access unit and, when the transfer instruction having a higher priority is received during the memory access, the memory access based on a low-priority transfer instruction is interrupted and starts the memory access based on the high-priority transfer instruction.

Information processing apparatus, memory control apparatus, and control method thereof

By connecting, to a bus bridge according to a configuration of a bus system, a monitor circuit including an activation control circuit generating a counter activation signal from an input monitor activation signal, a counter circuit, activated by the counter activation signal, counting the transfer number using a signal of bridge transfer completion indicating an issuance of one transfer from a bus bridge, and outputting a count completion signal when the transfers of the same number as that stuck in the bus bridge indicated by the signal of the transfer number stuck in the bridge is issued when being activated, and a completion control circuit outputting a monitor completion signal upon receiving the count completion signal from the counter circuit, consistency of data may be guaranteed in any bus system without changing the configuration of the bus bridge based on the number of masters accessing the bus bridge.

Monitor circuit, bus system, and bus bridge

Memory accesses to a memory device that is in a power saving mode depend on the order of the issuance thereof. Thus, a period of time during which the memory is placed in the power saving mode is sometimes shortened, resulting in less effective power savings. A memory control apparatus, which is connected with a plurality of masters and a plurality of memories having a power saving mode, arbitrates memory accesses from the plurality of the masters, monitors whether each of the plurality of the memories is in the power saving state, and determines the priorities of the memory accesses according to the result of the detection of the power saving mode.

Memory control apparatus and memory control method for controlling the priority of memory accesses

A memory access control device for controlling access to a plurality of memory devices with differing latency, controls, when performing a first access and then a second access, the timing of performing the second access, according to a memory device accessed in the first access and a memory device accessed in the second access.

Memory access control device, command issuing device, and method

An information processing system for performing processing of dividing a moving image into tiles and packetizing and outputting information corresponding to each tile includes a process time measuring packet generation unit adapted to generate and transmit a process time measuring packet in which a packet sending time is set to measure a packet process time, a packet process time measuring unit adapted to measure, based on the packet sending time set in the process time measuring packet and the reception time of the process time measuring packet, the packet process time necessary for processing a packet, a determination unit adapted to determine, based on the packet process time, the timestamp of the moving image divided into the tiles, and a packetization unit adapted to execute processing of packetizing and outputting the timestamp and the information of the moving image divided into the tiles.

Information processing system, information processing apparatus, information processing method, and program

A circuit configured to change a mode of a plurality of memory devices having a power saving mode includes a command queue configured to hold memory access, and a cancellation unit configured to cancel the power saving mode of target devices of the memory access held up to a predetermined stage of the command queue.

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Yokohama, Japan

Wataru Ochiai