Nec Corporation

Wataru Domon

Makoto Shibutani

Shuntaro Yamazaki

Jun-ichi Matsuda

A network synchronization method allows reduced frequency fluctuations due to synchronization control in a network. Each node connected to the network has time information individually varying in a period of T. A time master node periodically notifies its own time information to time slave devices. Each time slave node prepares update-possible time points having a period of T/N (N&#x3e;1). When receiving master time information, each time slave node updates its own time information using the master time information at an update-possible time point just after the master time information has been received.

Network synchronization technique

The invention provides, for an IEEE 1394 network wherein a plurality of IEEE 1394 serial buses are connected to each other by means of a bridge, a synchronization method between the buses wherein an existing 1394 apparatus operates even if it is connected to one of the buses and a band resource of the bus is not consumed. As a network cycle master which functions as a reference clock source of an entire network, an arbitrary one portal is selected. In each bus to which the network cycle master is not connected, a portal which has the least node hop number to the network cycle master is selected as a local cycle master. The other portals which are not selected are all set as a dependent portal. The network cycle master and the dependent portals transmit a synchronizing signal to the other portals in the same bridge. Each local cycle master receives the synchronizing signal transmitted from the network cycle master or the dependent portal in the same bridge and performs control of synchronizing the cycle frequency thereof with the cycle frequency of the portal which has transmitted the synchronizing signal. Each of the network cycle master and the local cycle masters operate as a cycle master in the bus to which it is connected.

Network synchronization system and network synchronization method

In a speed converter for an IEEE-1394 serial bus network, first and second communication device nodes are attached to first and second buses. A first transceiver node receives an inbound first packet at a first speed from the first bus and transmits an inbound second packet, which is received from the second bus by a second transceiver node at a second speed, as an outbound second packet at the first speed to the first bus. The second transceiver node transmits the inbound first packet as an outbound first packet at a second speed to the second bus. Header translation circuitry translates the destination identifier of the inbound first packet to the destination identifier of the outbound first packet according to a mapped relationship between the first transceiver node and the second communication node, and translates the destination identifier of the inbound second packet to the destination identifier of the outbound second packet.

Speed converter for IEEE-1394 serial bus network

An isochronous packet transfer method is provided which can reduce a transmit buffer size required for isochronous packet transfer, and which can give a constant delay to an isochronous packet even if transmission of a cycle start packet is delayed. An isochronous packet received from an input side bus is input to a delay section, and this isochronous packet is delayed in accordance with delay information and is transmitted to an output side bus. Input side and output side cycle identification information generating sections respectively output cycle identification information which changes at a timing at which a cycle start packet is sent to the input side bus and the output side bus. Input side and output side reference cycle identification information generating sections sample the input side and output side cycle identification information at predetermined timing and output input side and output side reference cycle identification information. A delay information generating section adds a fixed delay to a difference in the elapsed cycle number for each bus from the predetermined timing, based on input side and output side cycle identification information and input side and output side reference cycle identification information to generate delay information.

Isochronous packet transfer method, computer readable recording media recorded with control program for executing isochronous packet transfer, and bridge and packet transfer control LSI

A network configuration method ensuring high reliability of bridge manager selection and bus reset is disclosed. After configuring each of the IEEE 1394 buses according to IEEE 1394 standard, a network management node is selected from a first IEEE 1394 bus including at least one node capable of network management. First, the first IEEE 1394 bus is configured such that the first IEEE 1394 bus belongs to the network management node. Then, an adjacent IEEE 1394 bus of the first IEEE 1394 bus is configured into a configured IEEE 1394 bus to produce an interim network such that the adjacent IEEE 1394 bus belongs to the network management node. The configuration of the adjacent IEEE 1394 bus is repeated until no adjacent IEEE 1394 bus which does not belong to the network management node is left in the IEEE 1394 network.

Network configuration method

A connection controller for a serial bus network includes physical layer processing circuitry for performing the protocol of the physical layer of the network to establish communications with first, second and third nodes. The first node is specified as an initiator node and the second node is a target node of the first node. The physical layer processing circuitry is energized by power supplied from the first node. To reliably establish connections between desired nodes in a first-to-win racing environment, a delay time is introduced in response to the physical layer processing circuitry being energized. During the delay time, a logical connection is established between the first and second nodes and the third node is set in a disabled state.

Serial bus connection controller for establishing a logical connection between initiator and target nodes in a first-to-win racing condition

Disclosed is an optical network which has a plurality of subordinate optical networks, each of which being connected with a plurality of optical terminals which function as a transmitter and a receiver of a signal light, wherein multiplexing of transmission signals and demultiplexing of reception signals at the optical terminals are carried out in the subcarrier multiplexing manner; and a main optical network which is connected with the subordinate optical networks, wherein multiplexing of signal lights transmitted from the subordinate optical networks is carried out in the wavelength division multiplexing manner.

Optical network

An optical module for use in a subcarrier multiplexed (SCM) optical transmission system and capable of reducing the distortion of a signal light due to multiple reflections. A distortion reducing device is implemented by an optical fiber cable longer than the coherence length of the signal light and is located at each of signal input and output portions or each portion where optical devices are jointed together within the module.

Optical module for subcarrier multiplexed optical transmission system

The present invention provides a resonance-type optical receiver circuit which keeps predetermined small distortion even when the received light level becomes high. The resonance-type optical receiver circuit varies the resistance value of variable resistance element 80, which is used as a load resistor to optical detector 4, in response to the intensity of output signal 10 of an amplifier. The load resistor varies in response to a variations of the received light level of the optical detector in this manner to keep the input to the amplifier lower than a fixed value.

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Tokyo, Japan

Wataru Domon